SLLSEQ4C august   2015  – may 2023 ISO5452

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Pin Configuration and Function
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics
    10. 7.10 Switching Characteristics
    11. 7.11 Insulation Characteristics Curves
    12. 7.12 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Supply and Active Miller Clamp
      2. 9.3.2 Active Output Pull-down
      3. 9.3.3 Undervoltage Lockout (UVLO) with Ready (RDY) Pin Indication Output
      4. 9.3.4 Soft Turn-Off, Fault ( FLT) and Reset ( RST)
      5. 9.3.5 Short Circuit Clamp
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Recommended ISO5452 Application Circuit
        2. 10.2.2.2  FLT and RDY Pin Circuitry
        3. 10.2.2.3  Driving the Control Inputs
        4. 10.2.2.4  Local Shutdown and Reset
        5. 10.2.2.5  Global-Shutdown and Reset
        6. 10.2.2.6  Auto-Reset
        7. 10.2.2.7  DESAT Pin Protection
        8. 10.2.2.8  DESAT Diode and DESAT Threshold
        9. 10.2.2.9  Determining the Maximum Available, Dynamic Output Power, POD-max
        10. 10.2.2.10 Example
        11. 10.2.2.11 Higher Output Current Using an External Current Buffer
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 PCB Material
  14. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.10 Switching Characteristics

Over recommended operating conditions unless otherwise noted.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
trOutput signal rise time, see Figure 8-1, Figure 8-2, and Figure 8-3CLOAD = 1 nF1235ns
CLOAD = 1 nF, TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V18
tfOutput signal fall time, see Figure 8-1, Figure 8-2, and Figure 8-3CLOAD = 1 nF1237ns
CLOAD = 1 nF, TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V20
tPLH, tPHLPropagation delay, see Figure 8-1, Figure 8-2, and Figure 8-3CLOAD = 1 nF76110ns
CLOAD = 1 nF, TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
tsk-pPulse skew |tPHL – tPLH|, see Figure 8-1, Figure 8-2, and Figure 8-3CLOAD = 1 nF20ns
tsk-ppPart-to-part skew, see Figure 8-1, Figure 8-2, and Figure 8-3CLOAD = 1 nF30(1)ns
tGFGlitch filter on IN+, IN–, RST, see Figure 8-1, Figure 8-2, and Figure 8-3CLOAD = 1 nF2040ns
CLOAD = 1 nF, TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V30
tDS (90%)DESAT sense to 90% VOUTH/L delay, see Figure 8-1, Figure 8-2, and Figure 8-3CLOAD = 10 nF760ns
CLOAD = 10 nF, TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V553
tDS (10%)DESAT sense to 10% VOUTH/L delay, see Figure 8-1, Figure 8-2, and Figure 8-3CLOAD = 10 nF3.5μs
CLOAD = 10 nF, TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V2
tDS (GF)DESAT glitch filter delayCLOAD = 1 nF, TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V330ns
tDS ( FLT)DESAT sense to FLT-low delay, see Figure 8-31.4μs
tLEBLeading edge blanking time, see Figure 8-1and Figure 8-2310480ns
TA = 25°C, VCC1 = 5 V,
VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V		400
tGF(RSTFLT)Glitch filter on RST for resetting FLT300800ns
CIInput capacitance(2)VI = VCC1 / 2 + 0.4 × sin (2πft), f = 1 MHz, VCC1 = 5 V, TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V2pF
CMTICommon-mode transient immunity, see Figure 8-4VCM = 1500 V50kV/μs
VCM = 1500 V, TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V100
(1) Measured at same supply voltage and temperature condition
(2) Measured from input pin to ground.