SLLSEQ4C august   2015  – may 2023 ISO5452

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Pin Configuration and Function
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics
    10. 7.10 Switching Characteristics
    11. 7.11 Insulation Characteristics Curves
    12. 7.12 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Supply and Active Miller Clamp
      2. 9.3.2 Active Output Pull-down
      3. 9.3.3 Undervoltage Lockout (UVLO) with Ready (RDY) Pin Indication Output
      4. 9.3.4 Soft Turn-Off, Fault ( FLT) and Reset ( RST)
      5. 9.3.5 Short Circuit Clamp
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Recommended ISO5452 Application Circuit
        2. 10.2.2.2  FLT and RDY Pin Circuitry
        3. 10.2.2.3  Driving the Control Inputs
        4. 10.2.2.4  Local Shutdown and Reset
        5. 10.2.2.5  Global-Shutdown and Reset
        6. 10.2.2.6  Auto-Reset
        7. 10.2.2.7  DESAT Pin Protection
        8. 10.2.2.8  DESAT Diode and DESAT Threshold
        9. 10.2.2.9  Determining the Maximum Available, Dynamic Output Power, POD-max
        10. 10.2.2.10 Example
        11. 10.2.2.11 Higher Output Current Using an External Current Buffer
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 PCB Material
  14. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.9 Electrical Characteristics

Over recommended operating conditions unless otherwise noted.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VOLTAGE SUPPLY
VIT+(UVLO1)Positive-going UVLO1 threshold voltage input side (VCC1 – GND1)2.25V
VIT-(UVLO1)Negative-going UVLO1 threshold voltage input side (VCC1 – GND1)1.7V
VHYS(UVLO1)UVLO1 Hysteresis voltage (VIT+ – VIT–) input sideTA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V0.2V
VIT+(UVLO2)Positive-going UVLO2 threshold voltage output side (VCC2 – GND2)13V
TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V12
VIT-(UVLO2)Negative-going UVLO2 threshold voltage output side (VCC2 – GND2)9.5V
TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V11
VHYS(UVLO2)UVLO2 Hysteresis voltage (VIT+ – VIT–) output sideTA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V1V
IQ1Input supply quiescent current4.5mA
TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V2.8
IQ2Output supply quiescent current6mA
TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V3.6
LOGIC I/O
VIT+(IN, RST)Positive-going input threshold voltage (IN+, IN–, RST)0.7 × VCC1V
VIT-(IN, RST)Negative-going input threshold voltage (IN+, IN–, RST)0.3 × VCC1V
VHYS(IN, RST)Input hysteresis voltage (IN+, IN–, RST)TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V0.15 × VCC1V
IIHHigh-level input leakage at (IN+)(1)IN+ = VCC1, TA = 25°C, VCC1 = 5 V,
VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V		100µA
IILLow-level input leakage at (IN–, RST)(2)IN– = GND1, RST = GND1, TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V–100µA
IPUPullup current of FLT, RDYV(RDY) = GND1, V(FLT) = GND1, TA = 25°C,
VCC1 = 5 V, VCC2 – GND2 = 15 V,
GND2 – VEE2 = 8 V		100µA
VOLLow-level output voltage at FLT, RDYI(FLT) = 5 mA0.2V
GATE DRIVER STAGE
V(OUTPD)Active output pulldown voltageI(OUTH/L) = 200 mA, VCC2 = open2V
V(OUTH)High-level output voltageI(OUTH) = –20 mAVCC2 – 0.5V
I(OUTH) = –20 mA, TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 VVCC2 – 0.24
V(OUTL)Low-level output voltageI(OUTL) = 20 mAVEE2 + 50mV
I(OUTL) = 20 mA, TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 VVEE2 + 13
I(OUTH)High-level output peak currentIN+ = high, IN– = low, V(OUTH) = VCC2 – 15 V1.5A
IN+ = high, IN– = low, V(OUTH) = VCC2 – 15 V,
TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V		2.5
I(OUTL)Low-level output peak currentIN+ = low, IN– = high, V(OUTL) = VEE2 + 15 V3.4A
IN+ = low, IN– = high, V(OUTL) = VEE2 + 15 V,
TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V		5
I(OLF)Low level output current during fault conditionTA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V130mA
ACTIVE MILLER CLAMP
V(CLP)Low-level clamp voltageI(CLP) = 20 mAVEE2 + 0.08V
I(CLP) = 20 mA, TA = 25°C, VCC1 = 5 V,
VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V		VEE2 + 0.015
I(CLP)Low-level clamp currentV(CLAMP) = VEE2 + 2.5 V1.63.3A
V(CLAMP) = VEE2 + 2.5 V, TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V2.5
V(CLTH)Clamp threshold voltage1.62.5V
TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V2.1
SHORT CIRCUIT CLAMPING
V(CLP_OUTH)Clamping voltage
(VOUTH – VCC2)		IN+ = high, IN– = low, tCLP = 10 µs,
I(OUTH) = 500 mA		1.11.3V
IN+ = high, IN– = low, tCLP = 10 µs, I(OUTH) = 500 mA, TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
V(CLP_OUTL)Clamping voltage
(VOUTL – VCC2)		IN+ = high, IN– = low, tCLP = 10 µs,
I(OUTL) = 500 mA		1.31.5V
IN+ = high, IN– = low, tCLP = 10 µs, I(OUTL) = 500 mA, TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V
V(CLP_CLAMP)Clamping voltage
(VCLP – VCC2)		IN+ = high, IN– = low, tCLP = 10 µs, I(CLP) = 500 mA, TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V1.3V
Clamping voltage at CLAMPIN+ = High, IN– = Low, I(CLP) = 20 mA1.1V
IN+ = High, IN– = Low, I(CLP) = 20 mA, TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V,
GND2 – VEE2 = 8 V		0.7
V(CLP_OUTL)Clamping voltage at OUTL
(VCLP - VCC2)		IN+ = High, IN– = Low, I(OUTL) = 20 mA1.1V
IN+ = High, IN– = Low, I(OUTL) = 20 mA, TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V,
GND2 – VEE2 = 8 V		0.7
DESAT PROTECTION
I(CHG)Blanking capacitor charge currentV(DESAT) – GND2 = 2 V0.420.58mA
V(DESAT) – GND2 = 2 V, TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V0.5
I(DCHG)Blanking capacitor discharge currentV(DESAT) – GND2 = 6 V9mA
V(DESAT) – GND2 = 6 V, TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V14
V(DSTH)DESAT threshold voltage with respect to GND28.39.5V
TA = 25°C, VCC1 = 5 V, VCC2 – GND2 = 15 V, GND2 – VEE2 = 8 V9
V(DSL)DESAT voltage with respect to GND2, when OUTH/L is driven low0.41V
(1) IIH for IN–, RST pin is zero as they are pulled high internally.
(2) IIL for IN+ is zero, as it is pulled low internally.