Refer to the PDF data sheet for device specific package drawings
The ISO5851-Q1 is a 5.7-kVRMS, reinforced isolated gate driver for IGBTs and MOSFETs with 2.5-A source and 5-A sink current. The input side operates from a single 3-V to 5.5-V supply. The output side allows for a supply range from minimum 15 V to maximum 30 V. Two complementary CMOS inputs control the output state of the gate driver. The short propagation time of 76 ns assures accurate control of the output stage.
An internal desaturation (DESAT) fault detection recognizes when the IGBT is in an overload condition. Upon a DESAT detect, the gate driver output is driven low to VEE2 potential, turning the IGBT immediately off.
When desaturation is active, a fault signal is sent across the isolation barrier, pulling the FLT output at the input side low and blocking the isolator input. The FLT output condition is latched and can be reset through a low-active pulse at the RST input.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ISO5851-Q1 | SOIC (16) | 10.30 mm × 7.50 mm |
When the IGBT is turned off during normal operation with bipolar output supply, the output is hard clamp to VEE2. If the output supply is unipolar, an active Miller clamp can be used, allowing Miller current to sink across a low impedance path preventing IGBT to be dynamically turned on during high voltage transient conditions.
When desaturation is active, a fault signal is sent across the isolation barrier pulling the FLT output at the input side low and blocking the isolator input. The FLT output condition is latched and can be reset through a low-active pulse at the RST input.
When the IGBT is turned off during normal operation with bipolar output supply, the output is hard clamp to VEE2. If the output supply is unipolar, an active Miller clamp can be used, allowing Miller current to sink across a low impedance path preventing IGBT to be dynamically turned on during high voltage transient conditions.
The readiness for the gate driver to be operated is under the control of two undervoltage-lockout circuits monitoring the input side and output side supplies. If either side has insufficient supply the RDY output goes low; otherwise, this output is high.
The ISO5851-Q1 is available in a 16-pin SOIC package. Device operation is specified over a temperature range from –40°C to +125°C ambient.
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
CLAMP | 7 | O | Miller clamp output |
DESAT | 2 | I | Desaturation voltage input |
FLT | 13 | O | Fault output, low-active during DESAT condition |
GND1 | 9, 16 | — | Input ground |
GND2 | 3 | — | Gate drive common. Connect to IGBT emitter. |
IN+ | 10 | I | Non-inverting gate drive voltage control input |
IN– | 11 | I | Inverting gate drive voltage control input |
NC | 4 | — | Not connected |
OUT | 6 | O | Gate drive voltage output |
RDY | 12 | O | Power-good output, active high when both supplies are good. |
RST | 14 | I | Reset input, apply a low pulse to reset fault latch. |
VCC1 | 15 | — | Positive input supply (3 V to 5.5 V) |
VCC2 | 5 | — | Most positive output supply potential. |
VEE2 | 1, 8 | — | Output negative supply. Connect to GND2 for Unipolar supply application. |
MIN | MAX | UNIT | ||||
---|---|---|---|---|---|---|
VCC1 | Supply voltage input side | GND1 - 0.3 | 6 | V | ||
VCC2 | Positive supply voltage output side | VCC2 – GND2 | –0.3 | 35 | V | |
VEE2 | Negative supply voltage output side | VEE2 – GND2 | –17.5 | 0.3 | V | |
V(SUP2) | Total supply output voltage | VCC2 – VEE2 | –0.3 | 35 | V | |
VOUT | Gate driver output voltage | VEE2 – 0.3 | VCC2 + 0.3 | V | ||
I(OUTH) | Gate driver high output current | Gate driver high output current max pulse width = 10 μs, max duty cycle = 0.2% |
2.7 | A | ||
I(OUTL) | Gate driver low output current | Gate driver high output current max pulse width = 10 μs, max duty cycle = 0.2% |
5.5 | A | ||
V(LIP) | Voltage at IN+, IN–,FLT, RDY, RST | GND1 – 0.3 | VCC1 + 0.3 | V | ||
I(LOP) | Output current of FLT, RDY | 10 | mA | |||
V(DESAT) | Voltage at DESAT | GND2 – 0.3 | VCC2 + 0.3 | V | ||
V(CLAMP) | Clamp voltage | VEE2 – 0.3 | VCC2 + 0.3 | V | ||
TJ | Junction temperature | –40 | 150 | °C | ||
TSTG | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002(1) | ±4000 | V |
Charged-device model (CDM), per AEC Q100-011 | ±1500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VCC1 | Supply voltage input side | 3 | 5.5 | V | |
VCC2 | Positive supply voltage output side (VCC2 – GND2) | 15 | 30 | V | |
VEE2 | Negative supply voltage output side (VEE2 – GND2) | –15 | 0 | V | |
V(SUP2) | Total supply voltage output side (VCC2 – VEE2) | 15 | 30 | V | |
VIH | High-level input voltage (IN+, IN–, RST) | 0.7 × VCC1 | VCC1 | V | |
VIL | Low-level input voltage (IN+, IN–, RST) | 0 | 0.3 × VCC1 | V | |
tUI | Pulse width at IN+, IN– for full output (CLOAD = 1 nF) | 40 | ns | ||
tRST | Pulse width at RST for resetting fault latch | 800 | ns | ||
TA | Ambient temperature | –40 | 25 | 125 | °C |
THERMAL METRIC(1) | ISO5851-Q1 | UNIT | |
---|---|---|---|
DW (SOIC) | |||
16 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 99.6 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 48.5 | °C/W |
RθJB | Junction-to-board thermal resistance | 56.5 | °C/W |
ψJT | Junction-to-top characterization parameter | 29.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 56.5 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
PD | Maximum power dissipation(1) | 1255 | mW | |||
PID | Maximum input power dissipation | 175 | mW | |||
POD | Maximum output power dissipation | 1080 | mW |
PARAMETER | TEST CONDITIONS | SPECIFICATION | UNIT | |
---|---|---|---|---|
CLR | External clearance(1) | Shortest terminal-to-terminal distance through air | 8 | mm |
CPG | External creepage(1) | Shortest terminal-to-terminal distance across the package surface | 8 | mm |
DTI | Distance through the insulation | Minimum internal gap (internal clearance) | 21 | μm |
CTI | Comparative tracking index | DIN EN 60112 (VDE 0303-11); IEC 60112 | >600 | V |
Material group | According to IEC 60664-1 | I | ||
Overvoltage category per IEC 60664-1 | Rated mains voltage ≤ 600 VRMS | I-IV | ||
Rated mains voltage ≤ 1000 VRMS | I-III | |||
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12(2) | ||||
VIORM | Maximum repetitive peak isolation voltage | AC voltage (bipolar) | 2121 | VPK |
VIOWM | Maximum isolation working voltage | AC voltage. Time dependent dielectric breakdown (TDDB) Test, see Figure 1 | 1500 | VRMS |
DC voltage | 2121 | VDC | ||
VIOTM | Maximum Transient isolation voltage | VTEST = VIOTM, t = 60 sec (qualification), t = 1 sec (100% production) | 8000 | VPK |
VIOSM | Maximum surge isolation voltage(3) | Test method per IEC 60065, 1.2/50 μs waveform, VTEST = 1.6 x VIOSM = 12800 VPK (qualification) |
8000 | |
qpd | Apparent charge(4) | Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM = 2545 VPK, tm = 10 s |
≤5 | pC |
Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM = 3394 VPK, tm = 10 s |
≤5 | |||
Method b1: At routine test (100% production) and preconditioning (type test) Vini = VIOTM, tini = 60 s; Vpd(m) = 1.875× VIORM = 3977 VPK, tm = 10 s |
≤5 | |||
RIO | Isolation resistance, input to output(5) | VIO = 500 V at TS | > 109 | Ω |
VIO = 500 V, TA = 25°C | >1012 | Ω | ||
VIO = 500 V, 100°C ≤ TA ≤ 125°C | >1011 | Ω | ||
CIO | Barrier capacitance, input to output(5) | VIO = 0.4 x sin (2πft), f = 1 MHz | 1 | pF |
Pollution degree | 2 | |||
UL 1577 | ||||
VISO | Withstanding Isolation voltage | VTEST = VISO, t = 60 sec (qualification), VTEST = 1.2 × VISO = 6840 VRMS, t = 1 sec (100% production) |
5700 | VRMS |
VDE | CSA | UL | CQC | TUV |
---|---|---|---|---|
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN 60950-1 (VDE 0805 Teil 1):2011-01 |
Certified according to CSA Component Acceptance Notice 5A, IEC 60950-1, and IEC 60601-1 | Certified according to UL 1577 Component Recognition Program | Certified according to GB 4943.1-2011 | Certified according to EN 61010-1:2010 (3rd Ed) and EN 60950-1:2006/A11:2009/A1:2010/ A12:2011/A2:2013 |
Reinforced Insulation Maximum Transient isolation voltage, 8000 VPK; Maximum surge isolation voltage, 8000 VPK, Maximum repetitive peak isolation voltage, 2121 VPK |
Isolation Rating of 5700 VRMS; Reinforced insulation per CSA 60950-1- 07+A1+A2 and IEC 60950-1 (2nd Ed.), 800 VRMS max working voltage (pollution degree 2, material group I) ; 2 MOPP (Means of Patient Protection) per CSA 60601-1:14 and IEC 60601-1 Ed. 3.1, 250 VRMS (354 VPK) max working voltage |
Single Protection, 5700 VRMS (1) | Reinforced Insulation, Altitude ≤ 5000m, Tropical climate, 400 VRMS maximum working voltage | 5700 VRMS Reinforced insulation per EN 61010-1:2010 (3rd Ed) up to working voltage of 600 VRMS 5700 VRMS Reinforced insulation per EN 60950-1:2006/A11:2009/A1:2010/ A12:2011/A2:2013 up to working voltage of 800 VRMS |
Certification completed Certificate number: 40040142 |
Master contract number: 220991 | Certification completed File number: E181974 |
Certification completed Certificate number: CQC16001141761 |
Certification completed Client ID number: 77311 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
IS | Safety input, output or supply current | RθJA = 99.6°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C | 349 | mA | |||
RθJA = 99.6°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C | 228 | ||||||
RθJA = 99.6°C/W, VI = 15 V, TJ = 150°C, TA = 25°C | 84 | ||||||
RθJA = 99.6°C/W, VI = 30 V, TJ = 150°C, TA = 25°C | 42 | ||||||
PS | Safety input, output, or total power | RθJA = 99.6°C/W, TJ = 150°C, TA = 25°C | 1255(1) | mW | |||
TS | Maximum ambient safety temperature | 150 | °C |
The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOLTAGE SUPPLY | |||||||
VIT+(UVLO1) | Positive-going UVLO1 threshold voltage input side (VCC1 – GND1) | 2.25 | V | ||||
VIT-(UVLO1) | Negative-going UVLO1 threshold voltage input side (VCC1 – GND1) | 1.7 | V | ||||
VHYS(UVLO1) | UVLO1 Hysteresis voltage (VIT+ – VIT–) input side | 0.24 | V | ||||
VIT+(UVLO2) | Positive-going UVLO2 threshold voltage output side (VCC2 – GND2) | 12 | 13 | V | |||
VIT-(UVLO2) | Negative-going UVLO2 threshold voltage output side (VCC2 – GND2) | 9.5 | 11 | V | |||
VHYS(UVLO2) | UVLO2 Hysteresis voltage (VIT+ – VIT–) output side | 1 | V | ||||
IQ1 | Input supply quiescent current | 2.8 | 4.5 | mA | |||
IQ2 | Output supply quiescent current | 3.6 | 6 | mA | |||
LOGIC I/O | |||||||
VIT+(IN,RST) | Positive-going input threshold voltage (IN+, IN–, RST) | 0.7 × VCC1 | V | ||||
VIT-(IN,RST) | Negative-going input threshold voltage (IN+, IN–, RST) | 0.3 × VCC1 | V | ||||
VHYS(IN,RST) | Input hysteresis voltage (IN+, IN–, RST) | 0.15 × VCC1 | V | ||||
IIH | High-level input leakage at (IN+) | IN+ = VCC1 | 100 | µA | |||
IIL | Low-level input leakage at (IN–, RST) | IN– = GND1, RST = GND1 | –100 | µA | |||
IPU | Pull-up current of FLT, RDY | V(RDY) = GND1, V(FLT) = GND1 | 100 | µA | |||
VOL | Low-level output voltage at FLT, RDY | I(FLT) = 5 mA | 0.2 | V | |||
GATE DRIVER STAGE | |||||||
V(OUTPD) | Active output pulldown voltage | IOUT = 200 mA, VCC2 = open | 2 | V | |||
V(OUTH) | High-level output voltage | IOUT = –20 mA | VCC2 – 0.5 | VCC2 – 0.24 | V | ||
V(OUTL) | Low-level output voltage | IOUT = 20 mA | VEE2 + 13 | VEE2 + 50 | mV | ||
I(OUTH) | High-level output peak current | IN+ = high, IN– = low, VOUT = VCC2 - 15 V |
1.5 | 2.5 | A | ||
I(OUTL) | Low-level output peak current | IN+ = low, IN– = high, VOUT = VEE2 + 15 V |
3.4 | 5 | A | ||
ACTIVE MILLER CLAMP | |||||||
V(CLP) | Low-level clamp voltage | I(CLP) = 20 mA | VEE2 + 0.015 | VEE2 + 0.08 | V | ||
I(CLP) | Low-level clamp current | V(CLAMP) = VEE2 + 2.5 V | 1.6 | 2.5 | A | ||
V(CLTH) | Clamp threshold voltage | 1.6 | 2.1 | 2.5 | V | ||
SHORT CIRCUIT CLAMPING | |||||||
V(CLP_OUT) | Clamping voltage (VOUT - VCC2) |
IN+ = high, IN– = low, tCLP = 10 µs, I(OUTH) = 500 mA | 0.8 | 1.3 | V | ||
V(CLP_CLAMP) | Clamping voltage (VCLP - VCC2) |
IN+ = high, IN– = low, tCLP = 10 µs, I(CLP) = 500 mA | 1.3 | V | |||
V(CLP_CLAMP) | Clamping voltage at CLAMP | IN+ = High, IN– = Low, I(CLP) = 20 mA | 0.7 | 1.1 | V | ||
DESAT PROTECTION | |||||||
I(CHG) | Blanking capacitor charge current | V(DESAT) - GND2 = 2 V | 0.42 | 0.5 | 0.58 | mA | |
I(DCHG) | Blanking capacitor discharge current | V(DESAT) - GND2 = 6 V | 9 | 14 | mA | ||
V(DSTH) | DESAT threshold voltage with respect to GND2 | 8.3 | 9 | 9.5 | V | ||
V(DSL) | DESAT voltage with respect to GND2, when OUT is driven low | 0.4 | 1 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tr | Output signal rise time | CLOAD = 1 nF, see Figure 38, Figure 39, and Figure 40 | 12 | 20 | 35 | ns |
tf | Output signal fall time | 12 | 20 | 37 | ns | |
tPLH, tPHL | Propagation Delay | 76 | 110 | ns | ||
tsk-p | Pulse Skew |tPHL – tPLH| | 20 | ns | |||
tsk-pp | Part-to-part skew | 30(1) | ns | |||
tGF | Glitch filter on IN+, IN–, RST | 20 | 30 | 40 | ns | |
tDESAT (10%) | DESAT sense to 10% OUT delay | 300 | 415 | 500 | ns | |
tDESAT (GF) | DESAT glitch filter delay | 330 | ns | |||
tDESAT (FLT) | DESAT sense to FLT-low delay | see Figure 40 | 2000 | 2420 | ns | |
tLEB | Leading edge blanking time | see Figure 38 and Figure 39 | 330 | 400 | 500 | ns |
tGF(RSTFLT) | Glitch filter on RST for resetting FLT | 300 | 800 | ns | ||
CI | Input capacitance(2) | VI = VCC1 /2 + 0.4 x sin (2πft), f = 1 MHz, VCC1 = 5 V | 2 | pF | ||
CMTI | Common-mode transient immunity | VCM = 1500 V, see Figure 41 | 100 | 120 | kV/μs |
TA upto 150°C | Stress-voltage frequency = 60 Hz |
VCC2 = 30 V |
Unipolar: VCC2 – VEE2 = VCC2 – GND2 |
VCC2 = 30 V |
CL = 1 nF | RG = 0 Ω | |
VCC2 – VEE2 = VCC2 – GND2 = 20 V |
CL = 10 nF | RG = 0 Ω | |
VCC2 – VEE2 = VCC2 – GND2 = 20 V |
CL = 100 nF | RG = 0 Ω | |
VCC2 – VEE2 = VCC2 – GND2 = 20 V |
CL = 100 nF | RG = 10 Ω | |
VCC2 – VEE2 = VCC2 – GND2 = 20 V |
IN+ = Low | IN– = Low |
RG = 10 Ω, 20 kHz |
CL = 1 nF | RG = 0 Ω | VCC2 = 15 V |
RG = 0 Ω | VCC1 = 5 V |
RG = 10 Ω | VCC1 = 5 V |
CL = 1 nF |
VCC2 = 15 V | DESAT = 6 V |
CL = 1 nF | RG = 10 Ω | |
VCC2 – VEE2 = VCC2 – GND2 = 20 V |
CL = 10 nF | RG = 10 Ω | |
VCC2 – VEE2 = VCC2 – GND2 = 20 V |
CL = 100 nF | RG = 10 Ω | |
VCC2 – VEE2 = VCC2 – GND2 = 20 V |
IN+ = High | IN– = Low |
Input Frequency = 1 kHz |
no CL |
CL = 1nF | RG = 0 Ω | VCC1 = 5 V |
RG = 10 Ω | VCC1 = 5 V |
RG = 0 Ω | VCC1 = 5 V |
RG = 10 Ω | VCC1 = 5 V |
CL = 10 nF |