SLLSEQ2A September   2016  – December 2016 ISO5852S-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Function
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics
    10. 7.10 Switching Characteristics
    11. 7.11 Insulation Characteristics Curves
    12. 7.12 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Supply and Active Miller Clamp
      2. 9.3.2 Active Output Pulldown
      3. 9.3.3 Undervoltage Lockout (UVLO) With Ready (RDY) Pin Indication Output
      4. 9.3.4 Soft Turnoff, Fault (FLT) and Reset (RST)
      5. 9.3.5 Short Circuit Clamp
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Recommended ISO5852S-Q1 Application Circuit
        2. 10.2.2.2  FLT and RDY Pin Circuitry
        3. 10.2.2.3  Driving the Control Inputs
        4. 10.2.2.4  Local Shutdown and Reset
        5. 10.2.2.5  Global-Shutdown and Reset
        6. 10.2.2.6  Auto-Reset
        7. 10.2.2.7  DESAT Pin Protection
        8. 10.2.2.8  DESAT Diode and DESAT Threshold
        9. 10.2.2.9  Determining the Maximum Available, Dynamic Output Power, POD-max
        10. 10.2.2.10 Example
        11. 10.2.2.11 Higher Output Current Using an External Current Buffer
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 PCB Material
    3. 12.3 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Description (continued)

When desaturation is active, a fault signal is sent across the isolation barrier, pulling the FLT output at the input side low and blocking the isolator input. Mute logic is activated through the soft-turnoff period. The FLT output condition is latched and can be reset only after the RDY pin goes high, through a low-active pulse at the RST input.

When the IGBT is turned off during normal operation with a bipolar output supply, the output is hard clamp to VEE2. If the output supply is unipolar, an active Miller clamp can be used, allowing Miller current to sink across a low-impedance path which prevents the IGBT from dynamic turnon during high-voltage transient conditions.

The readiness for the gate driver to be operated is under the control of two undervoltage-lockout circuits monitoring the input-side and output-side supplies. If either side has insufficient supply, the RDY output goes low, otherwise this output is high.

The ISO5852S-Q1 device is available in a 16-pin SOIC package. Device operation is specified over a temperature range from –40°C to +125°C ambient.