SLLS918D July   2008  – November 2024 ISO721-Q1 , ISO722-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Recommended Operating Conditions
    3. 6.3  Thermal Information
    4. 6.4  Power Ratings
    5. 6.5  Insulation Specifications
    6. 6.6  Safety-Related Certifications
    7. 6.7  Safety Limiting Values
    8. 6.8  Electrical Characteristics: VCC1 and VCC2 5-V Operation
    9. 6.9  Electrical Characteristics: VCC1 and VCC2 at 3.3-V Operation
    10. 6.10 Electrical Characteristics: VCC1 at 3.3-V, VCC2 at 5-V Operation
    11. 6.11 Electrical Characteristics: VCC1 at 5-V, VCC2 at 3.3-V Operation
    12. 6.12 Switching Characteristics: VCC1 and VCC2 5-V Operation
    13. 6.13 Switching Characteristics: VCC1 and VCC2 at 3.3-V Operation
    14. 6.14 Switching Characteristics: VCC1 at 3.3-V, VCC2 at 5-V Operation
    15. 6.15 Switching Characteristics: VCC1 at 5-V, VCC2 at 3.3-V Operation
    16. 6.16 Typical Characteristics
    17. 6.17 Insulation Characteristics Curves
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Device Functional Modes
      1. 8.3.1 Device I/O Schematic
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 PCB Material
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Parameter Measurement Information

ISO721-Q1 ISO722-Q1 Switching Characteristic Test Circuit and Voltage Waveforms Figure 7-1 Switching Characteristic Test Circuit and Voltage Waveforms
ISO721-Q1 ISO722-Q1 ISO722-Q1 Sleep-Mode High-Level Output Test Circuit and Voltage WaveformsFigure 7-2 ISO722-Q1 Sleep-Mode High-Level Output Test Circuit and Voltage Waveforms
ISO721-Q1 ISO722-Q1 ISO722-Q1 Sleep-Mode Low-Level Output Test Circuit and Voltage WaveformsFigure 7-3 ISO722-Q1 Sleep-Mode Low-Level Output Test Circuit and Voltage Waveforms
Note:

A: The input pulse is supplied by a generator having the following characteristics:

PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.

B: CL = 15 pF ± 20% and includes instrumentation and fixture capacitance.

ISO721-Q1 ISO722-Q1 Failsafe Delay Time Test Circuit and Voltage Waveforms
NOTE: VI transition time is 100 ns.
Figure 7-4 Failsafe Delay Time Test Circuit and Voltage Waveforms
ISO721-Q1 ISO722-Q1 Common-Mode Transient-Immunity Test Circuit and Voltage Waveform
NOTE: Pass/fail criterion is no change in VO.
Figure 7-5 Common-Mode Transient-Immunity Test Circuit and Voltage Waveform
ISO721-Q1 ISO722-Q1 Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform
NOTE: Bit pattern run length is 216 – 1. Transition time is 800 ps. NRZ data input has no more than five consecutive 1s or 0s.
Figure 7-6 Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform