SLLS918D July   2008  – November 2024 ISO721-Q1 , ISO722-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Recommended Operating Conditions
    3. 6.3  Thermal Information
    4. 6.4  Power Ratings
    5. 6.5  Insulation Specifications
    6. 6.6  Safety-Related Certifications
    7. 6.7  Safety Limiting Values
    8. 6.8  Electrical Characteristics: VCC1 and VCC2 5-V Operation
    9. 6.9  Electrical Characteristics: VCC1 and VCC2 at 3.3-V Operation
    10. 6.10 Electrical Characteristics: VCC1 at 3.3-V, VCC2 at 5-V Operation
    11. 6.11 Electrical Characteristics: VCC1 at 5-V, VCC2 at 3.3-V Operation
    12. 6.12 Switching Characteristics: VCC1 and VCC2 5-V Operation
    13. 6.13 Switching Characteristics: VCC1 and VCC2 at 3.3-V Operation
    14. 6.14 Switching Characteristics: VCC1 at 3.3-V, VCC2 at 5-V Operation
    15. 6.15 Switching Characteristics: VCC1 at 5-V, VCC2 at 3.3-V Operation
    16. 6.16 Typical Characteristics
    17. 6.17 Insulation Characteristics Curves
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Device Functional Modes
      1. 8.3.1 Device I/O Schematic
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 PCB Material
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3 Thermal Information

THERMAL METRIC(1) UNIT
D (SOIC)
8 PINS
RθJA Junction-to-ambient thermal resistance Low-K Thermal Resistance(2) 212 °C/W
High-K Thermal Resistance 122
RθJC(top) Junction-to-case (top) thermal resistance 69.1 °C/W
RθJB Junction-to-board thermal resistance 47.7 °C/W
ψJT Junction-to-top characterization parameter 15.2 °C/W
ψJB Junction-to-board characterization parameter 47.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.
(2) Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages.