SLLS965E
July 2009 – November 2024
ISO7220A-Q1
,
ISO7221A-Q1
,
ISO7221C-Q1
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
Recommended Operating Conditions
5.3
Safety-Related Certifications
5.4
Thermal Information
5.5
Safety Limiting Values
5.6
Insulation Specifications
5.7
Electrical Characterstics
5.8
Electrical Characteristics
5.9
Electrical Characteristics
5.10
Electrical Charcteristics
5.11
Switching Characteristics
5.12
Switching Characteristics
5.13
Switching Characteristics
5.14
Switching Characteristics
5.15
Typical Characteristics
6
Parameter Measurement Information
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Insulation Lifetime
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.1.1
PCB Material
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Device Support
9.1.1
Development Support
9.2
Documentation Support
9.2.1
Related Documentation
9.3
Receiving Notification of Documentation Updates
9.4
Support Resources
9.5
Trademarks
9.6
Electrostatic Discharge Caution
9.7
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
D|8
MSOI002K
Thermal pad, mechanical data (Package|Pins)
Orderable Information
SLLS965E_pm
slls965e_oa
6
Parameter Measurement Information
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, t
r
≤ 3 ns, t
f
≤ 3 ns, Z
O
= 50 Ω.
B.
C
L
= 15 pF and includes instrumentation and fixture capacitance within ± 20%.
Figure 6-1
Switching Characteristic Test Circuit and Voltage Waveforms
A.
C
L
= 15 pF and includes instrumentation and fixture capacitance within ± 20%.
Figure 6-2
Failsafe Delay Time Test Circuit and Voltage Waveforms
A.
C
L
= 15 pF and includes instrumentation and fixture capacitance within ± 20%.
Figure 6-3
Common-Mode Transient Immunity Test Circuit
PRBS bit pattern run length is 2
16
– 1. Transition time is 800 ps.
Figure 6-4
Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform