A minimum of four layers is required to accomplish
a low EMI PCB design (see Figure 7-4). Layer stacking must be in the following order (top-to-bottom): high-speed
signal layer, ground plane, power plane and low-frequency signal layer.
- Routing the high-speed traces
on the top layer avoids the use of vias (and the introduction of the
inductances) and allows for clean interconnects between the isolator and the
transmitter and receiver circuits of the data link.
- Placing a solid ground plane
next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance
path for the return current flow.
- Placing the power plane next
to the ground plane creates additional high-frequency bypass capacitance of
approximately 100pF/in2.
- Routing the slower speed
control signals on the bottom layer allows for greater flexibility as these
signal links typically have margin to tolerate discontinuities such as
vias.
If an additional supply voltage plane or signal layer is needed, add a second
power/ground plane system to the stack to keep the planes symmetrical. This makes
the stack mechanically stable and prevents warping. Also the power and ground plane
of each power system can be placed closer together, thus increasing the
high-frequency bypass capacitance significantly. For detailed layout
recommendations, see Application Note
SLLA284,
Digital Isolator
Design Guide.