SLLS868U September   2007  – October 2024 ISO7240C , ISO7240CF , ISO7240M , ISO7241C , ISO7241M , ISO7242C , ISO7242M

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configurations and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics: VCC1 and VCC2 at 5-V Operation
    10. 5.10 Supply Current Characteristics: VCC1 and VCC2 at 5-V Operation
    11. 5.11 Electrical Characteristics: VCC1 at 5-V, VCC2 at 3.3-V Operation
    12. 5.12 Supply Current Characteristics: VCC1 at 5-V, VCC2 at 3.3-V Operation
    13. 5.13 Electrical Characteristics: VCC1 at 3.3-V, VCC2 at 5-V Operation
    14. 5.14 Supply Current Characteristics: VCC1 at 3.3-V, VCC2 at 5-V Operation
    15. 5.15 Electrical Characteristics: VCC1 and VCC2 at 3.3 V Operation
    16. 5.16 Supply Current Characteristics: VCC1 and VCC2 at 3.3 V Operation
    17. 5.17 Switching Characteristics: VCC1 and VCC2 at 5-V Operation
    18. 5.18 Switching Characteristics: VCC1 at 5-V, VCC2 at 3.3-V Operation
    19. 5.19 Switching Characteristics: VCC1 at 3.3-V and VCC2 at 5-V Operation
    20. 5.20 Switching Characteristics: VCC1 and VCC2 at 3.3-V Operation
    21. 5.21 Insulation Characteristics Curves
    22. 5.22 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device I/O Schematics
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Isolated Data Acquisition System for Process Control
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Isolated SPI for an Analog Input Module with 16 Inputs
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
      3. 8.2.3 Isolated RS-232 Interface
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 PCB Material
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Related Links
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Parameter Measurement Information

ISO7240CF ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M Switching Characteristic Test Circuit and Voltage Waveforms
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 6-1 Switching Characteristic Test Circuit and Voltage Waveforms
ISO7240CF ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M Enable or Disable Propagation-Delay Time Test Circuit and Waveform
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 6-2 Enable or Disable Propagation-Delay Time Test Circuit and Waveform
ISO7240CF ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M Failsafe Delay Time Test Circuit and Voltage Waveforms
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 6-3 Failsafe Delay Time Test Circuit and Voltage Waveforms
ISO7240CF ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M Wake Time From Input Disable Test Circuit and Voltage Waveforms
The test that yields the longest time is used in this data sheet.
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 6-4 Wake Time From Input Disable Test Circuit and Voltage Waveforms
ISO7240CF ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M Common-Mode Transient Immunity Test Circuit and Voltage Waveform
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
Figure 6-5 Common-Mode Transient Immunity Test Circuit and Voltage Waveform
ISO7240CF ISO7240C ISO7240M ISO7241C ISO7241M ISO7242C ISO7242M Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform
PRBS bit pattern run length is 216 – 1. Transition time is 800 ps. NRZ data input has no more than five consecutive 1s or 0s.
Figure 6-6 Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform