ISO733x-Q1 Robust EMC, Low Power, Triple-Channel Digital Isolators
- SLLSER7 November 2015 ISO7330-Q1 , ISO7331-Q1
  
  PRODUCTION DATA.

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DATA SHEET

ISO733x-Q1 Robust EMC, Low Power, Triple-Channel Digital Isolators

1 Features

Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
- Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature Range
- Device HBM Classification Level 3A
- Device CDM Classification Level C6
Signaling Rate: 25 Mbps
Integrated Noise Filter on the Inputs
Default Output High and Low Options
Low Power Consumption: Typical I_CC per Channel at 1 Mbps:
- ISO7330-Q1: 1 mA (5-V Supplies),
  0.8 mA (3.3-V Supplies)
- ISO7331-Q1: 1.4 mA (5-V Supplies),
  1 mA (3.3-V Supplies)
Low Propagation Delay: 32 ns
Typical (5-V Supplies)
Operates from 3.3 V and 5-V Supplies
3.3-V and 5-V Level Translation
70-kV/μs Transient Immunity,
Typical (5-V Supplies)
Robust Electromagnetic Compatibility (EMC)
- System-level ESD, EFT, and Surge Immunity
- Low Emissions
Wide Body SOIC-16 Package
Isolation Barrier Life: > 25 Years
Safety and Regulatory Approvals:
- 4242-V_PK Isolation per DIN V VDE V 0884-10 and DIN EN 61010-1
- 3000-V_RMS Isolation for 1 minute per UL 1577
- CSA Component Acceptance Notice 5A, IEC 60950-1 and IEC 61010-1 End Equipment Standards
- Planned CQC Certification per GB4943.1-2011

2 Applications

Opto-Coupler Replacement in:
- Industrial FieldBus
  - ProfiBus
  - ModBus
  - DeviceNet™ Data Buses
- Servo Control Interface
- Motor Control
- Power Supplies
- Battery Packs

3 Description

The ISO733x-Q1 family of devices provides galvanic isolation up to 3000 V_RMS for 1 minute per UL 1577 and 4242 V_PKper VDE V 0884-10. These devices have three isolated channels comprised of logic input and output buffers separated by a silicon dioxide (SiO₂) insulation barrier.

The ISO7330-Q1 has all three channels in the same direction while ISO7331-Q1 has two channels in forward and one channel in reverse direction. In case of input power or signal loss, the default output is low for orderable part numbers with suffix F and high for orderable part numbers without suffix F. See the Device Functional Modes section for further details.

Used in conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. The ISO733x-Q1 family of devices has integrated noise filter for harsh industrial environment where short noise pulses may be present at the device input pins. The ISO733x-Q1 family of devices has TTL input thresholds and operates from 3-V to 5.5-V supply levels. Through innovative chip design and layout techniques, electromagnetic compatibility of the ISO733x-Q1 family of devices has been significantly enhanced to enable system-level ESD, EFT, Surge and Emissions compliance.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
ISO7330-Q1	SOIC (16)	10.30 mm × 7.50 mm
ISO7331-Q1	SOIC (16)	10.30 mm × 7.50 mm

For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Schematic

V_CCI and GNDI are supply and ground connections respectively for the input channels.

V_CCO and GNDO are supply and ground connections respectively for the output.

4 Revision History

DATE	REVISION	NOTES
November 2015	*	Initial release.

5 Pin Configuration and Functions

ISO7330-Q1 DW Package

16-Pin SOIC

Top View

ISO7330-Q1 ISO7331-Q1 po_iso7330C_sllsek9.gif

ISO7331-Q1 DW Package

16-Pin SOIC

Top View

ISO7330-Q1 ISO7331-Q1 po_iso7331C_sllsek9.gif

Pin Functions

PIN			I/O	DESCRIPTION
NAME	NO.
NAME	ISO7330-Q1	ISO7331-Q1
EN	10	—	I	Output enable. OUTA, OUTB, and OUTC are enabled when EN is high or disconnected and disabled when EN is low.
EN1	—	7	I	Output enable 1. OUTC is enabled when EN1 is high or disconnected and disabled when EN1 is low.
EN2	—	10	I	Output enable 2. OUTA and OUTB are enabled when EN2 is high or disconnected and disabled when EN2 is low.
GND1	2	2	—	Ground connection for V_CC1
GND1	8	8	—	Ground connection for V_CC1
GND2	9	9	—	Ground connection for V_CC2
GND2	15	15	—	Ground connection for V_CC2
INA	3	3	I	Input, channel A
INB	4	4	I	Input, channel B
INC	5	12	I	Input, channel C
NC	6	6	—	No Connect. These pins have no internal connection.
	7	6
	11	11
OUTA	14	14	O	Output, channel A
OUTB	13	13	O	Output, channel B
OUTC	12	5	O	Output, channel C
V_CC1	1	1	—	Power supply, V_CC1
V_CC2	16	16	—	Power supply, V_CC2

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
V_CC	Supply voltage⁽²⁾	V_CC1 , V_CC2	–0.5	6	V
	Voltage ⁽²⁾	INx, OUTx, ENx	–0.5	V_CC+0.5⁽³⁾	V
I_O	Output current			±15	mA
T_J	Junction temperature			150	°C
T_stg	Storage temperature		–65	150	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal and are peak voltage values.

(3) Maximum voltage must not exceed 6 V.

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾		±4000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per AEC Q100-011		±1500	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

		MIN	NOM	MAX	UNIT
V_CC1, V_CC2	Supply voltage	3		5.5	V
I_OH	High-level output current	–4			mA
I_OL	Low-level output current			4	mA
V_IH	High-level input voltage	2		5.5	V
V_IL	Low-level input voltage	0		0.8	V
t_ui	Input pulse duration	40			ns
1 / t_ui	Signaling rate	0		25	Mbps
T_J	Junction temperature⁽¹⁾			136	°C
T_A	Ambient temperature	–40	25	125	°C

(1) To maintain the recommended operating conditions for T_J, see the Thermal Information table.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		ISO733x-Q1	UNIT
		DW (SOIC)
		16 PINS
R_θ_JA	Junction-to-ambient thermal resistance	78.3	°C/W
R_θJCtop	Junction-to-case (top) thermal resistance	40.9	°C/W
R_θJB	Junction-to-board thermal resistance	42.9	°C/W
ψ_JT	Junction-to-top characterization parameter	15.3	°C/W
ψ_JB	Junction-to-board characterization parameter	42.4	°C/W
R_θJCbot	Junction-to-case (bottom) thermal resistance	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics—5-V Supply

V_CC1 and V_CC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	I_OH = –4 mA; see Figure 11	V_CCO⁽¹⁾– 0.5	4.7		V
V_OH	High-level output voltage	I_OH= –20 μA; see Figure 11	V_CCO⁽¹⁾ – 0.1	5		V
V_OL	Low-level output voltage	I_OL = 4 mA; see Figure 11		0.2	0.4	V
V_OL	Low-level output voltage	I_OL = 20 μA; see Figure 11		0	0.1	V
V_I(HYS)	Input threshold voltage hysteresis			480		mV
I_IH	High-level input current	IN = V_CC			10	μA
I_IL	Low-level input current	IN = 0 V	–10			μA
CMTI	Common-mode transient immunity	V_I = V_CC or 0 V; see Figure 14.	25	70		kV/μs

(1) V_CCO is supply voltage, V_CC1 or V_CC2, for the output channel being measured.

6.6 Supply Current Characteristics—5-V Supply

All inputs switching with square wave clock signal for dynamic I_CC measurement. V_CC1 and V_CC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS		SUPPLY CURRENT	TYP	MAX	UNIT
ISO7330-Q1
	Supply current for V_CC1 and V_CC2	Disable	V_I = V_CC or 0 V, EN = 0 V	I_CC1	0.5	1.1	mA
		Disable	V_I = V_CC or 0 V, EN = 0 V	I_CC2	0.4	0.9
		DC to 1 Mbps	DC Input: V_I = V_CC or 0 V, AC Input: C_L = 15 pF	I_CC1	0.5	1.1
		DC to 1 Mbps	DC Input: V_I = V_CC or 0 V, AC Input: C_L = 15 pF	I_CC2	2.6	4.2
		10 Mbps	C_L = 15 pF	I_CC1	1.1	1.9
		10 Mbps	C_L = 15 pF	I_CC2	4.3	6
		25 Mbps	C_L = 15 pF	I_CC1	2.1	3.3
		25 Mbps	C_L = 15 pF	I_CC2	7	9.3
ISO7331-Q1
	Supply current for V_CC1 and V_CC2	Disable	V_I = V_CC or 0 V, EN1 = EN2 = 0 V	I_CC1	0.7	1.6	mA
		Disable	V_I = V_CC or 0 V, EN1 = EN2 = 0 V	I_CC2	0.7	1.3
		DC to 1 Mbps	DC Input: V_I = V_CC or 0 V, AC Input: C_L = 15 pF	I_CC1	1.8	3
		DC to 1 Mbps	DC Input: V_I = V_CC or 0 V, AC Input: C_L = 15 pF	I_CC2	2.4	3.6
		10 Mbps	C_L = 15 pF	I_CC1	2.8	4.1
		10 Mbps	C_L = 15 pF	I_CC2	3.8	5.1
		25 Mbps	C_L = 15 pF	I_CC1	4.3	6.2
		25 Mbps	C_L = 15 pF	I_CC2	5.8	7.8

6.7 Electrical Characteristics—3.3-V Supply

V_CC1 and V_CC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	I_OH = –4 mA; see Figure 11	V_CCO⁽¹⁾ – 0.5	3		V
V_OH	High-level output voltage	I_OH= –20 μA; see Figure 11	V_CCO⁽¹⁾ – 0.1	3.3		V
V_OL	Low-level output voltage	I_OL = 4 mA; see Figure 11		0.2	0.4	V
V_OL	Low-level output voltage	I_OL = 20 μA; see Figure 11		0	0.1	V
V_I(HYS)	Input threshold voltage hysteresis			425		mV
I_IH	High-level input current	IN = V_CC			10	μA
I_IL	Low-level input curre	IN = 0 V	–10			μA
CMTI	Common-mode transient immunity	V_I = V_CC or 0 V; see Figure 14	25	50		kV/μs

(1) V_CCO is supply voltage, V_CC1 or V_CC2, for the output channel being measured.

6.8 Supply Current Characteristics—3.3-V Supply

All inputs switching with square wave clock signal for dynamic I_CC measurement. V_CC1 and V_CC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS		SUPPLY CURRENT	TYP	MAX	UNIT
ISO7330-Q1
	Supply current for V_CC1 and V_CC2	Disable	V_I = V_CC or 0 V, EN = 0 V	I_CC1	0.3	0.6	mA
		Disable	V_I = V_CC or 0 V, EN = 0 V	I_CC2	0.3	0.6
		DC to 1 Mbps	DC Input: V_I = V_CC or 0 V, AC Input: C_L = 15 pF	I_CC1	0.3	0.6
		DC to 1 Mbps	DC Input: V_I = V_CC or 0 V, AC Input: C_L = 15 pF	I_CC2	2	3.1
		10 Mbps	C_L = 15 pF	I_CC1	0.7	1.1
		10 Mbps	C_L = 15 pF	I_CC2	3.1	4.3
		25 Mbps	C_L = 15 pF	I_CC1	1.2	2
		25 Mbps	C_L = 15 pF	I_CC2	4.8	6.3
ISO7331-Q1
	Supply current for V_CC1 and V_CC2	Disable	V_I = V_CC or 0 V, EN = 0 V	I_CC1	0.5	0.9	mA
		Disable	V_I = V_CC or 0 V, EN = 0 V	I_CC2	0.5	0.8
		DC to 1 Mbps	DC Input: V_I = V_CC or 0 V, AC Input: C_L = 15 pF	I_CC1	1.3	2.1
		DC to 1 Mbps	DC Input: V_I = V_CC or 0 V, AC Input: C_L = 15 pF	I_CC2	1.7	2.6
		10 Mbps	C_L = 15 pF	I_CC1	1.9	2.7
		10 Mbps	C_L = 15 pF	I_CC2	2.6	3.5
		25 Mbps	C_L = 15 pF	I_CC1	2.9	4.2
		25 Mbps	C_L = 15 pF	I_CC2	3.9	5.2

6.9 Power Dissipation Characteristics

V_CC1 = V_CC2 = 5.5 V, T_J = 150°C, C_L = 15 pF, Input a 12.5-MHz 50% duty cycle square wave (unless otherwise noted)

PARAMETER		MAX	UNIT
P_D	Maximum Power Dissipation by ISO7330-Q1	70	mW
P_D1	Maximum Power Dissipation by Side-1 of ISO7330-Q1	20	mW
P_D2	Maximum Power Dissipation by Side-2 of ISO7330-Q1	50	mW
P_D	Maximum Power Dissipation by ISO7331-Q1	84	mW
P_D1	Maximum Power Dissipation by Side-1 of ISO7331-Q1	35	mW
P_D2	Maximum Power Dissipation by Side-2 of ISO7331-Q1	49	mW

6.10 Switching Characteristics—5-V Supply

V_CC1 and V_CC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_PLH, t_PHL	Propagation delay time		See Figure 11	20	32	58	ns
PWD⁽¹⁾	Pulse width distortion \|t_PHL – t_PLH\|		See Figure 11			4	ns
t_sk(o)⁽²⁾	Channel-to-channel output skew time		Same direction channels			2.5	ns
t_sk(o)⁽²⁾	Channel-to-channel output skew time		Opposite direction channels			17	ns
t_sk(pp) ⁽³⁾	Part-to-part skew time					23	ns
t_r	Output signal rise time		See Figure 11		3		ns
t_f	Output signal fall time		See Figure 11		2		ns
t_PHZ	Disable propagation delay, high-to-high impedance output		See Figure 12		7	12	ns
t_PLZ	Disable propagation delay, low-to-high impedance output		See Figure 12		7	12	ns
t_PZH	Enable propagation delay, high impedance-to-high output	ISO733xCQDWQ1 and ISO733xCQDWRQ1	See Figure 12		7	12	ns
t_PZH	Enable propagation delay, high impedance-to-high output	ISO733xFCQDWQ1 and ISO733xFCQDWRQ1	See Figure 12		11000	23000⁽⁴⁾	ns
t_PZL	Enable propagation delay, high impedance-to-low output	ISO733xCQDWQ1 and ISO733xCQDWRQ1	See Figure 12		11000	23000⁽⁴⁾	ns
t_PZL	Enable propagation delay, high impedance-to-low output	ISO733xFCQDWQ1 and ISO733xFCQDWRQ1	See Figure 12		7	12	ns
t_fs	Fail-safe output delay time from input power loss		See Figure 13		7		μs

(1) Also known as pulse skew.

(2) t_sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.

(3) t_sk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

(4) The enable signal rate should be ≤ 43 Kbps

6.11 Switching Characteristics—3.3-V Supply

V_CC1 and V_CC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_PLH, t_PHL	Propagation delay time		See Figure 11	22	36	66	ns
PWD⁽¹⁾	Pulse width distortion \|t_PHL – t_PLH\|		See Figure 11			2.5	ns
t_sk(o)⁽²⁾	Channel-to-channel output skew time		Same direction channels			3	ns
t_sk(o)⁽²⁾	Channel-to-channel output skew time		Opposite direction channels			16	ns
t_sk(pp) ⁽³⁾	Part-to-part skew time					27	ns
t_r	Output signal rise time		See Figure 11		3		ns
t_f	Output signal fall time		See Figure 11		2		ns
t_PHZ	Disable propagation delay, high-to-high impedance output		See Figure 12		9	18	ns
t_PLZ	Disable propagation delay, low-to-high impedance output		See Figure 12		9	18	ns
t_PZH	Enable propagation delay, high impedance-to-high output	ISO733xCQDWQ1 and ISO733xCQDWRQ1	See Figure 12		9	18	ns
t_PZH	Enable propagation delay, high impedance-to-high output	ISO733xFCQDWQ1 and ISO733xFCQDWRQ1	See Figure 12		13000	24000⁽⁴⁾	ns
t_PZL	Enable propagation delay, high impedance-to-low output	ISO733xCQDWQ1 and ISO733xCQDWRQ1	See Figure 12		13000	24000⁽⁴⁾	ns
t_PZL	Enable propagation delay, high impedance-to-low output	ISO733xFCQDWQ1 and ISO733xFCQDWRQ1	See Figure 12		9	18	ns
t_fs	Fail-safe output delay time from input power loss		See Figure 13		7		μs

(1) Also known as pulse skew.

(2) t_sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.

(4) The enable signal rate should be ≤ 41 Kbps

6.12 Typical Characteristics

T_A = 25°C

C_L = 15 pF

Figure 1. ISO7330-Q1 Supply Current vs Data Rate
(With 15-pF Load)

T_A = 25°C

C_L = 15 pF

Figure 3. ISO7331-Q1 Supply Current vs Data Rate
(With 15-pF Load)

T_A = 25°C

Figure 5. High-Level Output Voltage vs High-level Output Current

Figure 7. Power Supply Undervoltage Threshold vs Free-Air Temperature

Figure 9. Input Glitch Suppression Time vs Free-Air Temperature

T_A = 25°C

C_L = No Load

Figure 2. ISO7330-Q1 Supply Current vs Data Rate
(With No Load)

T_A = 25°C

C_L = No Load

Figure 4. ISO7331-Q1 Supply Current vs Data Rate
(With No Load)

T_A = 25°C

Figure 6. Low-Level Output Voltage vs Low-Level Output Current

Figure 8. Propagation Delay Time vs Free-Air Temperature

T_A = 25°C

Figure 10. Output Jitter vs Data Rate

7 Parameter Measurement Information

ISO7330-Q1 ISO7331-Q1 switch_test_circuit_sllsek9.gif

A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, t_r ≤ 3 ns, t_f ≤ 3 ns, Z_O = 50 Ω. At the input, a 50-Ω resistor is required to terminate the Input Generator signal. It is not needed in actual application.

B. C_L = 15 pF and includes instrumentation and fixture capacitance within ±20%.

Figure 11. Switching Characteristic Test Circuit and Voltage Waveforms

ISO7330-Q1 ISO7331-Q1 delay_tim_llsek9.gif

A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 10 kHz, 50% duty cycle,
t_r ≤ 3 ns, t_f ≤ 3 ns, Z_O = 50 Ω.

B. C_L = 15 pF and includes instrumentation and fixture capacitance within ±20%.

Figure 12. Enable and Disable Propagation Delay Time Test Circuit and Waveform

ISO7330-Q1 ISO7331-Q1 failsafe_sllsek9.gif

A. C_L = 15 pF and includes instrumentation and fixture capacitance within ±20%.

Figure 13. Fail-Safe Output Delay-Time Test Circuit and Voltage Waveforms

ISO7330-Q1 ISO7331-Q1 com_tran_imm_test_circ_sllsek9.gif

A. C_L = 15 pF and includes instrumentation and fixture capacitance within ±20%.

Figure 14. Common-Mode Transient Immunity Test Circuit