SLLSER7 November   2015 ISO7330-Q1 , ISO7331-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics—5-V Supply
    6. 6.6  Supply Current Characteristics—5-V Supply
    7. 6.7  Electrical Characteristics—3.3-V Supply
    8. 6.8  Supply Current Characteristics—3.3-V Supply
    9. 6.9  Power Dissipation Characteristics
    10. 6.10 Switching Characteristics—5-V Supply
    11. 6.11 Switching Characteristics—3.3-V Supply
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 High Voltage Feature Description
        1. 8.3.1.1 Package Insulation Specifications
        2. 8.3.1.2 Insulation Characteristics
        3. 8.3.1.3 Regulatory Information
        4. 8.3.1.4 Safety Limiting Values
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device I/O Schematics
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Typical Supply Current Equations
          1. 9.2.1.1.1 ISO7330-Q1
          2. 9.2.1.1.2 ISO7321-Q1
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Electromagnetic Compatibility (EMC) Considerations
      3. 9.2.3 Application Curves
      4. 9.2.4 Systems Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Community Resource
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage(2) VCC1 , VCC2 –0.5 6 V
Voltage (2) INx, OUTx, ENx –0.5 VCC+0.5(3) V
IO Output current ±15 mA
TJ Junction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal and are peak voltage values.
(3) Maximum voltage must not exceed 6 V.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±4000 V
Charged-device model (CDM), per AEC Q100-011 ±1500
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC1, VCC2 Supply voltage 3 5.5 V
IOH High-level output current –4 mA
IOL Low-level output current 4 mA
VIH High-level input voltage 2 5.5 V
VIL Low-level input voltage 0 0.8 V
tui Input pulse duration 40 ns
1 / tui Signaling rate 0 25 Mbps
TJ Junction temperature(1) 136 °C
TA Ambient temperature –40 25 125 °C
(1) To maintain the recommended operating conditions for TJ, see the Thermal Information table.

6.4 Thermal Information

THERMAL METRIC(1) ISO733x-Q1 UNIT
DW (SOIC)
16 PINS
RθJA Junction-to-ambient thermal resistance 78.3 °C/W
RθJCtop Junction-to-case (top) thermal resistance 40.9 °C/W
RθJB Junction-to-board thermal resistance 42.9 °C/W
ψJT Junction-to-top characterization parameter 15.3 °C/W
ψJB Junction-to-board characterization parameter 42.4 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics—5-V Supply

VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –4 mA; see Figure 11 VCCO(1)– 0.5 4.7 V
IOH = –20 μA; see Figure 11 VCCO(1) – 0.1 5
VOL Low-level output voltage IOL = 4 mA; see Figure 11 0.2 0.4 V
IOL = 20 μA; see Figure 11 0 0.1
VI(HYS) Input threshold voltage hysteresis 480 mV
IIH High-level input current IN = VCC 10 μA
IIL Low-level input current IN = 0 V –10 μA
CMTI Common-mode transient immunity VI = VCC or 0 V; see Figure 14. 25 70 kV/μs
(1) VCCO is supply voltage, VCC1 or VCC2, for the output channel being measured.

6.6 Supply Current Characteristics—5-V Supply

All inputs switching with square wave clock signal for dynamic ICC measurement. VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS SUPPLY CURRENT MIN TYP MAX UNIT
ISO7330-Q1
Supply current for VCC1 and VCC2 Disable VI = VCC or 0 V, EN = 0 V ICC1 0.5 1.1 mA
ICC2 0.4 0.9
DC to 1 Mbps DC Input: VI = VCC or 0 V,
AC Input: CL = 15 pF		 ICC1 0.5 1.1
ICC2 2.6 4.2
10 Mbps CL = 15 pF ICC1 1.1 1.9
ICC2 4.3 6
25 Mbps CL = 15 pF ICC1 2.1 3.3
ICC2 7 9.3
ISO7331-Q1
Supply current for VCC1 and VCC2 Disable VI = VCC or 0 V, EN1 = EN2 = 0 V ICC1 0.7 1.6 mA
ICC2 0.7 1.3
DC to 1 Mbps DC Input: VI = VCC or 0 V,
AC Input: CL = 15 pF		 ICC1 1.8 3
ICC2 2.4 3.6
10 Mbps CL = 15 pF ICC1 2.8 4.1
ICC2 3.8 5.1
25 Mbps CL = 15 pF ICC1 4.3 6.2
ICC2 5.8 7.8

6.7 Electrical Characteristics—3.3-V Supply

VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –4 mA; see Figure 11 VCCO(1) – 0.5 3 V
IOH = –20 μA; see Figure 11 VCCO(1) – 0.1 3.3
VOL Low-level output voltage IOL = 4 mA; see Figure 11 0.2 0.4 V
IOL = 20 μA; see Figure 11 0 0.1
VI(HYS) Input threshold voltage hysteresis 425 mV
IIH High-level input current IN = VCC 10 μA
IIL Low-level input curre IN = 0 V –10 μA
CMTI Common-mode transient immunity VI = VCC or 0 V; see Figure 14 25 50 kV/μs
(1) VCCO is supply voltage, VCC1 or VCC2, for the output channel being measured.

6.8 Supply Current Characteristics—3.3-V Supply

All inputs switching with square wave clock signal for dynamic ICC measurement. VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS SUPPLY CURRENT MIN TYP MAX UNIT
ISO7330-Q1
Supply current for VCC1 and VCC2 Disable VI = VCC or 0 V, EN = 0 V ICC1 0.3 0.6 mA
ICC2 0.3 0.6
DC to 1 Mbps DC Input: VI = VCC or 0 V,
AC Input: CL = 15 pF		 ICC1 0.3 0.6
ICC2 2 3.1
10 Mbps CL = 15 pF ICC1 0.7 1.1
ICC2 3.1 4.3
25 Mbps CL = 15 pF ICC1 1.2 2
ICC2 4.8 6.3
ISO7331-Q1
Supply current for VCC1 and VCC2 Disable VI = VCC or 0 V, EN = 0 V ICC1 0.5 0.9 mA
ICC2 0.5 0.8
DC to 1 Mbps DC Input: VI = VCC or 0 V,
AC Input: CL = 15 pF		 ICC1 1.3 2.1
ICC2 1.7 2.6
10 Mbps CL = 15 pF ICC1 1.9 2.7
ICC2 2.6 3.5
25 Mbps CL = 15 pF ICC1 2.9 4.2
ICC2 3.9 5.2

6.9 Power Dissipation Characteristics

VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 12.5-MHz 50% duty cycle square wave (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PD Maximum Power Dissipation by ISO7330-Q1 70 mW
PD1 Maximum Power Dissipation by Side-1 of ISO7330-Q1 20 mW
PD2 Maximum Power Dissipation by Side-2 of ISO7330-Q1 50 mW
PD Maximum Power Dissipation by ISO7331-Q1 84 mW
PD1 Maximum Power Dissipation by Side-1 of ISO7331-Q1 35 mW
PD2 Maximum Power Dissipation by Side-2 of ISO7331-Q1 49 mW

6.10 Switching Characteristics—5-V Supply

VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 11 20 32 58 ns
PWD(1) Pulse width distortion |tPHL – tPLH| See Figure 11 4 ns
tsk(o)(2) Channel-to-channel output skew time Same direction channels 2.5 ns
Opposite direction channels 17
tsk(pp) (3) Part-to-part skew time 23 ns
tr Output signal rise time See Figure 11 3 ns
tf Output signal fall time See Figure 11 2 ns
tPHZ Disable propagation delay, high-to-high impedance output See Figure 12 7 12 ns
tPLZ Disable propagation delay, low-to-high impedance output See Figure 12 7 12 ns
tPZH Enable propagation delay, high impedance-to-high output ISO733xCQDWQ1 and ISO733xCQDWRQ1 See Figure 12 7 12 ns
ISO733xFCQDWQ1 and ISO733xFCQDWRQ1 11000 23000(4)
tPZL Enable propagation delay, high impedance-to-low output ISO733xCQDWQ1 and ISO733xCQDWRQ1 See Figure 12 11000 23000(4) ns
ISO733xFCQDWQ1 and ISO733xFCQDWRQ1 7 12
tfs Fail-safe output delay time from input power loss See Figure 13 7 μs
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.
(4) The enable signal rate should be ≤ 43 Kbps

6.11 Switching Characteristics—3.3-V Supply

VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 11 22 36 66 ns
PWD(1) Pulse width distortion |tPHL – tPLH| See Figure 11 2.5 ns
tsk(o)(2) Channel-to-channel output skew time Same direction channels 3 ns
Opposite direction channels 16
tsk(pp) (3) Part-to-part skew time 27 ns
tr Output signal rise time See Figure 11 3 ns
tf Output signal fall time See Figure 11 2 ns
tPHZ Disable propagation delay, high-to-high impedance output See Figure 12 9 18 ns
tPLZ Disable propagation delay, low-to-high impedance output See Figure 12 9 18 ns
tPZH Enable propagation delay, high impedance-to-high output ISO733xCQDWQ1 and ISO733xCQDWRQ1 See Figure 12 9 18 ns
ISO733xFCQDWQ1 and ISO733xFCQDWRQ1 13000 24000(4)
tPZL Enable propagation delay, high impedance-to-low output ISO733xCQDWQ1 and ISO733xCQDWRQ1 See Figure 12 13000 24000(4) ns
ISO733xFCQDWQ1 and ISO733xFCQDWRQ1 9 18
tfs Fail-safe output delay time from input power loss See Figure 13 7 μs
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.
(4) The enable signal rate should be ≤ 41 Kbps

6.12 Typical Characteristics

ISO7330-Q1 ISO7331-Q1 D001_SLLSEK9.gif
TA = 25°C CL = 15 pF
Figure 1. ISO7330-Q1 Supply Current vs Data Rate
(With 15-pF Load)
ISO7330-Q1 ISO7331-Q1 D003_SLLSEK9.gif
TA = 25°C CL = 15 pF
Figure 3. ISO7331-Q1 Supply Current vs Data Rate
(With 15-pF Load)
ISO7330-Q1 ISO7331-Q1 D005_SLLSEK9.gif
TA = 25°C
Figure 5. High-Level Output Voltage vs High-level Output Current
ISO7330-Q1 ISO7331-Q1 D007_SLLSEK9.gif
Figure 7. Power Supply Undervoltage Threshold vs Free-Air Temperature
ISO7330-Q1 ISO7331-Q1 D009_SLLSEK9.gif
Figure 9. Input Glitch Suppression Time vs Free-Air Temperature
ISO7330-Q1 ISO7331-Q1 D002_SLLSEK9.gif
TA = 25°C CL = No Load
Figure 2. ISO7330-Q1 Supply Current vs Data Rate
(With No Load)
ISO7330-Q1 ISO7331-Q1 D004_SLLSEK9.gif
TA = 25°C CL = No Load
Figure 4. ISO7331-Q1 Supply Current vs Data Rate
(With No Load)
ISO7330-Q1 ISO7331-Q1 D006_SLLSEK9.gif
TA = 25°C
Figure 6. Low-Level Output Voltage vs Low-Level Output Current
ISO7330-Q1 ISO7331-Q1 D008_SLLSEK9.gif
Figure 8. Propagation Delay Time vs Free-Air Temperature
ISO7330-Q1 ISO7331-Q1 D010_SLLSEK9.gif
TA = 25°C
Figure 10. Output Jitter vs Data Rate