ISO733x provide galvanic isolation up to 3000 VRMS for 1 minute per UL and 4242 VPK per VDE. These devices have three isolated channels comprised of logic input and output buffers separated by a silicon dioxide (SiO2) insulation barrier. ISO7330 has all three channels in the same direction while ISO7331 has two channels in forward and one channel in reverse direction. In case of input power or signal loss, default output is 'low' for devices with suffix 'F' and 'high' for devices without suffix 'F'. Used in conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. ISO733x has integrated noise filter for harsh industrial environment where short noise pulses may be present at the device input pins. ISO733x has TTL input thresholds and operates from 3 V to 5.5 V supply levels. Through innovative chip design and layout techniques, electromagnetic compatibility of ISO733x has been significantly enhanced to enable system-level ESD, EFT, Surge and Emissions compliance.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ISO7330C | SOIC (16) | 10,3mm x 7,5mm |
ISO7330FC | ||
ISO7331C | ||
ISO7331FC |
Changes from A Revision (April 2015) to B Revision
Changes from * Revision (January 2015) to A Revision
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | ISO7330 | ISO7331 | ||
VCC1 | 1 | 1 | – | Power supply, VCC1 |
VCC2 | 16 | 16 | – | Power supply, VCC2 |
GND1 | 2, 8 | 2, 8 | – | Ground connection for VCC1 |
GND2 | 9, 15 | 9, 15 | – | Ground connection for VCC2 |
INA | 3 | 3 | I | Input, channel A |
INB | 4 | 4 | I | Input, channel B |
INC | 5 | 12 | I | Input, channel C |
NC | 6, 7, 11 | 6, 11 | – | No Connect. These pins have no internal connection. |
OUTA | 14 | 14 | O | Output, channel A |
OUTB | 13 | 13 | O | Output, channel B |
OUTC | 12 | 5 | O | Output, channel C |
EN | 10 | – | I | Output enable. OUTA, OUTB, and OUTC are enabled when EN is high or disconnected and disabled when EN is low. |
EN1 | – | 7 | I | Output enable 1. OUTC is enabled when EN1 is high or disconnected and disabled when EN1 is low. |
EN2 | – | 10 | I | Output enable 2. OUTA and OUTB are enabled when EN2 is high or disconnected and disabled when EN2 is low. |
MIN | MAX | UNIT | ||||
---|---|---|---|---|---|---|
Supply voltage(2) | VCC1 , VCC2 | –0.5 | 6 | V | ||
Voltage (2) | INx, OUTx, ENx | –0.5 | VCC+0.5(3) | V | ||
Output current, IO | ±15 | mA | ||||
Junction temperature, TJ | 150 | °C | ||||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
VESD | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±4000 | V | |
Charged device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 | V |
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
VCC1, VCC2 | Supply voltage | 3 | 5.5 | V | |
IOH | High-level output current | –4 | mA | ||
IOL | Low-level output current | 4 | mA | ||
VIH | High-level input voltage | 2 | 5.5 | V | |
VIL | Low-level input voltage | 0 | 0.8 | V | |
tui | Input pulse duration | 40 | ns | ||
1 / tui | Signaling rate | 0 | 25 | Mbps | |
TJ(1) | Junction temperature | 136 | °C | ||
TA | Ambient temperature | -40 | 25 | 125 | °C |
THERMAL METRIC(1) | DW PACKAGE | UNIT | ||
---|---|---|---|---|
(16) PINS | ||||
RθJA | Junction-to-ambient thermal resistance | 78.3 | °C/W | |
RθJCtop | Junction-to-case (top) thermal resistance | 40.9 | ||
RθJB | Junction-to-board thermal resistance | 42.9 | ||
ψJT | Junction-to-top characterization parameter | 15.3 | ||
ψJB | Junction-to-board characterization parameter | 42.4 | ||
RθJCbot | Junction-to-case (bottom) thermal resistance | N/A | ||
PD (ISO7330) | Maximum Power Dissipation by ISO7330 | VCC1 = VCC2 = 5.5V, TJ = 150°C, CL = 15pF, Input a 12.5 MHz 50% duty cycle square wave | 70 | mW |
PD1 (ISO7330) | Maximum Power Dissipation by Side-1 of ISO7330 | 20 | ||
PD2 (ISO7330) | Maximum Power Dissipation by Side-2 of ISO7330 | 50 | ||
PD (ISO7331) | Maximum Power Dissipation by ISO7331 | VCC1 = VCC2 = 5.5V, TJ = 150°C, CL = 15pF, Input a 12.5 MHz 50% duty cycle square wave | 84 | mW |
PD1 (ISO7331) | Maximum Power Dissipation by Side-1 of ISO7331 | 35 | ||
PD2 (ISO7331) | Maximum Power Dissipation by Side-2 of ISO7331 | 49 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH = –4 mA; see Figure 11 | VCCO(1)– 0.5 | 4.7 | V | ||
IOH = –20 μA; see Figure 11 | VCCO(1) – 0.1 | 5 | |||||
VOL | Low-level output voltage | IOL = 4 mA; see Figure 11 | 0.2 | 0.4 | V | ||
IOL = 20 μA; see Figure 11 | 0 | 0.1 | |||||
VI(HYS) | Input threshold voltage hysteresis | 480 | mV | ||||
IIH | High-level input current | IN = VCC | 10 | μA | |||
IIL | Low-level input current | IN = 0 V | –10 | μA | |||
CMTI | Common-mode transient immunity | VI = VCC or 0 V; see Figure 14. | 25 | 70 | kV/μs | ||
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement) | |||||||
ISO7330 | |||||||
ICC1 | Supply current for VCC1 and VCC2 | Disable | VI = VCC or 0 V, EN = 0 V |
0.5 | 1.1 | mA | |
ICC2 | 0.4 | 0.9 | |||||
ICC1 | DC to 1 Mbps | DC Input: VI = VCC or 0 V, AC Input: CL = 15pF |
0.5 | 1.1 | |||
ICC2 | 2.6 | 4.2 | |||||
ICC1 | 10 Mbps | CL = 15pF | 1.1 | 1.9 | |||
ICC2 | 4.3 | 6 | |||||
ICC1 | 25 Mbps | CL = 15pF | 2.1 | 3.3 | |||
ICC2 | 7 | 9.3 | |||||
ISO7331 | |||||||
ICC1 | Supply current for VCC1 and VCC2 | Disable | VI = VCC or 0 V, EN1 = EN2 = 0 V |
0.7 | 1.6 | mA | |
ICC2 | 0.7 | 1.3 | |||||
ICC1 | DC to 1 Mbps | DC Input: VI = VCC or 0 V, AC Input: CL = 15pF |
1.8 | 3 | |||
ICC2 | 2.4 | 3.6 | |||||
ICC1 | 10 Mbps | CL = 15pF | 2.8 | 4.1 | |||
ICC2 | 3.8 | 5.1 | |||||
ICC1 | 25 Mbps | CL = 15pF | 4.3 | 6.2 | |||
ICC2 | 5.8 | 7.8 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH = –4 mA; see Figure 11 | VCCO(1)– 0.5 | 3 | V | ||
IOH = –20 μA; see Figure 11 | VCCO(1)– 0.1 | 3.3 | |||||
VOL | Low-level output voltage | IOL = 4 mA; see Figure 11 | 0.2 | 0.4 | V | ||
IOL = 20 μA; see Figure 11 | 0 | 0.1 | |||||
VI(HYS) | Input threshold voltage hysteresis | 425 | mV | ||||
IIH | High-level input current | IN = VCC | 10 | μA | |||
IIL | Low-level input curre | IN = 0 V | -10 | μA | |||
CMTI | Common-mode transient immunity | VI = VCC or 0 V; see Figure 14 | 25 | 50 | kV/μs | ||
SUPPLY CURRENT(All inputs switching with square wave clock signal for dynamic ICC measurement) | |||||||
ISO7330 | |||||||
ICC1 | Supply current for VCC1 and VCC2 | Disable | VI = VCC or 0 V, EN = 0 V |
0.3 | 0.6 | mA | |
ICC2 | 0.3 | 0.6 | |||||
ICC1 | DC to 1 Mbps | DC Input: VI = VCC or 0 V, AC Input: CL = 15pF |
0.3 | 0.6 | |||
ICC2 | 2 | 3.1 | |||||
ICC1 | 10 Mbps | CL = 15pF | 0.7 | 1.1 | |||
ICC2 | 3.1 | 4.3 | |||||
ICC1 | 25 Mbps | CL = 15pF | 1.2 | 2 | |||
ICC2 | 4.8 | 6.3 | |||||
ISO7331 | |||||||
ICC1 | Supply current for VCC1 and VCC2 | Disable | VI = VCC or 0 V, EN = 0 V |
0.5 | 0.9 | mA | |
ICC2 | 0.5 | 0.8 | |||||
ICC1 | DC to 1 Mbps | DC Input: VI = VCC or 0 V, AC Input: CL = 15pF |
1.3 | 2.1 | |||
ICC2 | 1.7 | 2.6 | |||||
ICC1 | 10 Mbps | CL = 15pF | 1.9 | 2.7 | |||
ICC2 | 2.6 | 3.5 | |||||
ICC1 | 25 Mbps | CL = 15pF | 2.9 | 4.2 | |||
ICC2 | 3.9 | 5.2 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
tPLH, tPHL | Propagation delay time | See Figure 11 | 20 | 32 | 58 | ns | |
PWD(1) | Pulse width distortion |tPHL – tPLH| | 4 | ns | ||||
tsk(o)(2) | Channel-to-channel output skew time | Same direction channels | 2.5 | ns | |||
Opposite direction channels | 17 | ||||||
tsk(pp)(3) | Part-to-part skew time | 23 | ns | ||||
tr | Output signal rise time | See Figure 11 | 3 | ns | |||
tf | Output signal fall time | 2 | ns | ||||
tPHZ | Disable propagation delay, high-to-high impedance output | See Figure 12 | 7 | 12 | ns | ||
tPLZ | Disable propagation delay, low-to-high impedance output | 7 | 12 | ||||
tPZH | Enable propagation delay, high impedance-to-high output | ISO733xC | 7 | 12 | |||
ISO733xFC | 11000 | 23000(4) | |||||
tPZL | Enable propagation delay, high impedance-to-low output | ISO733xC | 11000 | 23000(4) | |||
ISO733xFC | 7 | 12 | |||||
tfs | Fail-safe output delay time from input power loss | See Figure 13 | 7 | μs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
tPLH, tPHL | Propagation delay time | See Figure 11 | 22 | 36 | 66 | ns | |
PWD(1) | Pulse width distortion |tPHL – tPLH| | 2.5 | ns | ||||
tsk(o)(2) | Channel-to-channel output skew time | Same direction channels | 3 | ns | |||
Opposite direction channels | 16 | ||||||
tsk(pp)(3) | Part-to-part skew time | 27 | ns | ||||
tr | Output signal rise time | See Figure 11 | 3 | ns | |||
tf | Output signal fall time | 2 | ns | ||||
tPHZ | Disable propagation delay, high-to-high impedance output | See Figure 12 | 9 | 18 | ns | ||
tPLZ | Disable propagation delay, low-to-high impedance output | 9 | 18 | ||||
tPZH | Enable propagation delay, high impedance-to-high output | ISO733xC | 9 | 18 | |||
ISO733xFC | 13000 | 24000(4) | |||||
tPZL | Enable propagation delay, high impedance-to-low output | ISO733xC | 13000 | 24000(4) | |||
ISO733xFC | 9 | 18 | |||||
tfs | Fail-safe output delay time from input power loss | See Figure 13 | 7 | μs |
TA = 25°C | CL = 15 pF |
TA = 25°C | CL = 15 pF |
TA = 25°C |
TA = 25°C | CL = No Load |
TA = 25°C | CL = No Load |
TA = 25°C |
TA = 25°C |