ISO733x provide galvanic isolation up to 3000 VRMS for 1 minute per UL and 4242 VPK per VDE. These devices have three isolated channels comprised of logic input and output buffers separated by a silicon dioxide (SiO2) insulation barrier. ISO7330 has all three channels in the same direction while ISO7331 has two channels in forward and one channel in reverse direction. In case of input power or signal loss, default output is 'low' for devices with suffix 'F' and 'high' for devices without suffix 'F'. Used in conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. ISO733x has integrated noise filter for harsh industrial environment where short noise pulses may be present at the device input pins. ISO733x has TTL input thresholds and operates from 3 V to 5.5 V supply levels. Through innovative chip design and layout techniques, electromagnetic compatibility of ISO733x has been significantly enhanced to enable system-level ESD, EFT, Surge and Emissions compliance.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ISO7330C | SOIC (16) | 10,3mm x 7,5mm |
ISO7330FC | ||
ISO7331C | ||
ISO7331FC |
Changes from A Revision (April 2015) to B Revision
Changes from * Revision (January 2015) to A Revision
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | ISO7330 | ISO7331 | ||
VCC1 | 1 | 1 | – | Power supply, VCC1 |
VCC2 | 16 | 16 | – | Power supply, VCC2 |
GND1 | 2, 8 | 2, 8 | – | Ground connection for VCC1 |
GND2 | 9, 15 | 9, 15 | – | Ground connection for VCC2 |
INA | 3 | 3 | I | Input, channel A |
INB | 4 | 4 | I | Input, channel B |
INC | 5 | 12 | I | Input, channel C |
NC | 6, 7, 11 | 6, 11 | – | No Connect. These pins have no internal connection. |
OUTA | 14 | 14 | O | Output, channel A |
OUTB | 13 | 13 | O | Output, channel B |
OUTC | 12 | 5 | O | Output, channel C |
EN | 10 | – | I | Output enable. OUTA, OUTB, and OUTC are enabled when EN is high or disconnected and disabled when EN is low. |
EN1 | – | 7 | I | Output enable 1. OUTC is enabled when EN1 is high or disconnected and disabled when EN1 is low. |
EN2 | – | 10 | I | Output enable 2. OUTA and OUTB are enabled when EN2 is high or disconnected and disabled when EN2 is low. |
MIN | MAX | UNIT | ||||
---|---|---|---|---|---|---|
Supply voltage(2) | VCC1 , VCC2 | –0.5 | 6 | V | ||
Voltage (2) | INx, OUTx, ENx | –0.5 | VCC+0.5(3) | V | ||
Output current, IO | ±15 | mA | ||||
Junction temperature, TJ | 150 | °C | ||||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
VESD | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±4000 | V | |
Charged device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 | V |
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
VCC1, VCC2 | Supply voltage | 3 | 5.5 | V | |
IOH | High-level output current | –4 | mA | ||
IOL | Low-level output current | 4 | mA | ||
VIH | High-level input voltage | 2 | 5.5 | V | |
VIL | Low-level input voltage | 0 | 0.8 | V | |
tui | Input pulse duration | 40 | ns | ||
1 / tui | Signaling rate | 0 | 25 | Mbps | |
TJ(1) | Junction temperature | 136 | °C | ||
TA | Ambient temperature | -40 | 25 | 125 | °C |
THERMAL METRIC(1) | DW PACKAGE | UNIT | ||
---|---|---|---|---|
(16) PINS | ||||
RθJA | Junction-to-ambient thermal resistance | 78.3 | °C/W | |
RθJCtop | Junction-to-case (top) thermal resistance | 40.9 | ||
RθJB | Junction-to-board thermal resistance | 42.9 | ||
ψJT | Junction-to-top characterization parameter | 15.3 | ||
ψJB | Junction-to-board characterization parameter | 42.4 | ||
RθJCbot | Junction-to-case (bottom) thermal resistance | N/A | ||
PD (ISO7330) | Maximum Power Dissipation by ISO7330 | VCC1 = VCC2 = 5.5V, TJ = 150°C, CL = 15pF, Input a 12.5 MHz 50% duty cycle square wave | 70 | mW |
PD1 (ISO7330) | Maximum Power Dissipation by Side-1 of ISO7330 | 20 | ||
PD2 (ISO7330) | Maximum Power Dissipation by Side-2 of ISO7330 | 50 | ||
PD (ISO7331) | Maximum Power Dissipation by ISO7331 | VCC1 = VCC2 = 5.5V, TJ = 150°C, CL = 15pF, Input a 12.5 MHz 50% duty cycle square wave | 84 | mW |
PD1 (ISO7331) | Maximum Power Dissipation by Side-1 of ISO7331 | 35 | ||
PD2 (ISO7331) | Maximum Power Dissipation by Side-2 of ISO7331 | 49 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH = –4 mA; see Figure 11 | VCCO(1)– 0.5 | 4.7 | V | ||
IOH = –20 μA; see Figure 11 | VCCO(1) – 0.1 | 5 | |||||
VOL | Low-level output voltage | IOL = 4 mA; see Figure 11 | 0.2 | 0.4 | V | ||
IOL = 20 μA; see Figure 11 | 0 | 0.1 | |||||
VI(HYS) | Input threshold voltage hysteresis | 480 | mV | ||||
IIH | High-level input current | IN = VCC | 10 | μA | |||
IIL | Low-level input current | IN = 0 V | –10 | μA | |||
CMTI | Common-mode transient immunity | VI = VCC or 0 V; see Figure 14. | 25 | 70 | kV/μs | ||
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement) | |||||||
ISO7330 | |||||||
ICC1 | Supply current for VCC1 and VCC2 | Disable | VI = VCC or 0 V, EN = 0 V |
0.5 | 1.1 | mA | |
ICC2 | 0.4 | 0.9 | |||||
ICC1 | DC to 1 Mbps | DC Input: VI = VCC or 0 V, AC Input: CL = 15pF |
0.5 | 1.1 | |||
ICC2 | 2.6 | 4.2 | |||||
ICC1 | 10 Mbps | CL = 15pF | 1.1 | 1.9 | |||
ICC2 | 4.3 | 6 | |||||
ICC1 | 25 Mbps | CL = 15pF | 2.1 | 3.3 | |||
ICC2 | 7 | 9.3 | |||||
ISO7331 | |||||||
ICC1 | Supply current for VCC1 and VCC2 | Disable | VI = VCC or 0 V, EN1 = EN2 = 0 V |
0.7 | 1.6 | mA | |
ICC2 | 0.7 | 1.3 | |||||
ICC1 | DC to 1 Mbps | DC Input: VI = VCC or 0 V, AC Input: CL = 15pF |
1.8 | 3 | |||
ICC2 | 2.4 | 3.6 | |||||
ICC1 | 10 Mbps | CL = 15pF | 2.8 | 4.1 | |||
ICC2 | 3.8 | 5.1 | |||||
ICC1 | 25 Mbps | CL = 15pF | 4.3 | 6.2 | |||
ICC2 | 5.8 | 7.8 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH = –4 mA; see Figure 11 | VCCO(1)– 0.5 | 3 | V | ||
IOH = –20 μA; see Figure 11 | VCCO(1)– 0.1 | 3.3 | |||||
VOL | Low-level output voltage | IOL = 4 mA; see Figure 11 | 0.2 | 0.4 | V | ||
IOL = 20 μA; see Figure 11 | 0 | 0.1 | |||||
VI(HYS) | Input threshold voltage hysteresis | 425 | mV | ||||
IIH | High-level input current | IN = VCC | 10 | μA | |||
IIL | Low-level input curre | IN = 0 V | -10 | μA | |||
CMTI | Common-mode transient immunity | VI = VCC or 0 V; see Figure 14 | 25 | 50 | kV/μs | ||
SUPPLY CURRENT(All inputs switching with square wave clock signal for dynamic ICC measurement) | |||||||
ISO7330 | |||||||
ICC1 | Supply current for VCC1 and VCC2 | Disable | VI = VCC or 0 V, EN = 0 V |
0.3 | 0.6 | mA | |
ICC2 | 0.3 | 0.6 | |||||
ICC1 | DC to 1 Mbps | DC Input: VI = VCC or 0 V, AC Input: CL = 15pF |
0.3 | 0.6 | |||
ICC2 | 2 | 3.1 | |||||
ICC1 | 10 Mbps | CL = 15pF | 0.7 | 1.1 | |||
ICC2 | 3.1 | 4.3 | |||||
ICC1 | 25 Mbps | CL = 15pF | 1.2 | 2 | |||
ICC2 | 4.8 | 6.3 | |||||
ISO7331 | |||||||
ICC1 | Supply current for VCC1 and VCC2 | Disable | VI = VCC or 0 V, EN = 0 V |
0.5 | 0.9 | mA | |
ICC2 | 0.5 | 0.8 | |||||
ICC1 | DC to 1 Mbps | DC Input: VI = VCC or 0 V, AC Input: CL = 15pF |
1.3 | 2.1 | |||
ICC2 | 1.7 | 2.6 | |||||
ICC1 | 10 Mbps | CL = 15pF | 1.9 | 2.7 | |||
ICC2 | 2.6 | 3.5 | |||||
ICC1 | 25 Mbps | CL = 15pF | 2.9 | 4.2 | |||
ICC2 | 3.9 | 5.2 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
tPLH, tPHL | Propagation delay time | See Figure 11 | 20 | 32 | 58 | ns | |
PWD(1) | Pulse width distortion |tPHL – tPLH| | 4 | ns | ||||
tsk(o)(2) | Channel-to-channel output skew time | Same direction channels | 2.5 | ns | |||
Opposite direction channels | 17 | ||||||
tsk(pp)(3) | Part-to-part skew time | 23 | ns | ||||
tr | Output signal rise time | See Figure 11 | 3 | ns | |||
tf | Output signal fall time | 2 | ns | ||||
tPHZ | Disable propagation delay, high-to-high impedance output | See Figure 12 | 7 | 12 | ns | ||
tPLZ | Disable propagation delay, low-to-high impedance output | 7 | 12 | ||||
tPZH | Enable propagation delay, high impedance-to-high output | ISO733xC | 7 | 12 | |||
ISO733xFC | 11000 | 23000(4) | |||||
tPZL | Enable propagation delay, high impedance-to-low output | ISO733xC | 11000 | 23000(4) | |||
ISO733xFC | 7 | 12 | |||||
tfs | Fail-safe output delay time from input power loss | See Figure 13 | 7 | μs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
tPLH, tPHL | Propagation delay time | See Figure 11 | 22 | 36 | 66 | ns | |
PWD(1) | Pulse width distortion |tPHL – tPLH| | 2.5 | ns | ||||
tsk(o)(2) | Channel-to-channel output skew time | Same direction channels | 3 | ns | |||
Opposite direction channels | 16 | ||||||
tsk(pp)(3) | Part-to-part skew time | 27 | ns | ||||
tr | Output signal rise time | See Figure 11 | 3 | ns | |||
tf | Output signal fall time | 2 | ns | ||||
tPHZ | Disable propagation delay, high-to-high impedance output | See Figure 12 | 9 | 18 | ns | ||
tPLZ | Disable propagation delay, low-to-high impedance output | 9 | 18 | ||||
tPZH | Enable propagation delay, high impedance-to-high output | ISO733xC | 9 | 18 | |||
ISO733xFC | 13000 | 24000(4) | |||||
tPZL | Enable propagation delay, high impedance-to-low output | ISO733xC | 13000 | 24000(4) | |||
ISO733xFC | 9 | 18 | |||||
tfs | Fail-safe output delay time from input power loss | See Figure 13 | 7 | μs |
TA = 25°C | CL = 15 pF |
TA = 25°C | CL = 15 pF |
TA = 25°C |
TA = 25°C | CL = No Load |
TA = 25°C | CL = No Load |
TA = 25°C |
TA = 25°C |
The isolator in Figure 15 is based on a capacitive isolation barrier technique. The I/O channel of the device consists of two internal data channels, a high-frequency (HF) channel with a bandwidth from 100 kbps up to 25 Mbps, and a low-frequency (LF) channel covering the range from 100 kbps down to DC.
In principle, a single-ended input signal entering the HF channel is split into a differential signal via the inverter gate at the input. The following capacitor-resistor networks differentiate the signal into transient pulses, which then are converted into CMOS levels by a comparator. The transient pulses at the input of the comparator can be either above or below the common mode voltage VREF depending on whether the input bit transitioned from 0 to 1 or 1 to 0. The comparator threshold is adjusted based on the expected bit transition. A decision logic (DCL) at the output of the HF channel comparator measures the durations between signal transients. If the duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency signal), the DCL forces the output-multiplexer to switch from the high-frequency to the low-frequency channel.
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a sufficiently high frequency, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output multiplexer.
PRODUCT | CHANNEL DIRECTION | RATED ISOLATION | MAX DATA RATE | DEFAULT OUTPUT |
---|---|---|---|---|
ISO7330C | 3 Forward, 0 Reverse |
3000 VRMS / 4242 VPK(1) | 25 Mbps | High |
ISO7330FC | Low | |||
ISO7331C | 2 Forward, 1 Reverse |
High | ||
ISO7331FC | Low |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
L(I01) | Minimum air gap (clearance) | Shortest terminal-to-terminal distance through air | 8 | mm | |||
L(I02) | Minimum external tracking (creepage) | Shortest terminal-to-terminal distance across the package surface | 8 | mm | |||
CTI | Tracking resistance (comparative tracking index) | DIN EN 60112 (VDE 0303-11); IEC 60112 | >400 | V | |||
DTI | Minimum internal gap (internal clearance) | Distance through the insulation | 13 | µm | |||
RIO | Isolation resistance, input to output(1) | VIO = 500 V, TA = 25°C | >1012 | Ω | |||
VIO = 500 V, 100°C ≤ TA ≤ max | >1011 | Ω | |||||
CIO | Isolation capacitance, input to output(1) | VIO = 0.4 sin (2πft), f = 1 MHz | 2 | pF | |||
CI | Input capacitance(2) | VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V | 2 | pF |
NOTE
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance.
Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
PARAMETER(1) | TEST CONDITIONS | SPECIFICATION | UNIT | |
---|---|---|---|---|
VIOWM | Maximum isolation working voltage | 1000 | VRMS | |
VIORM | Maximum repetitive peak voltage per DIN V VDE V 0884-10 |
1414 | VPK | |
VPR | Input-to-output test voltage per DIN V VDE V 0884-10 |
After Input/Output safety test subgroup 2/3, VPR = VIORM x 1.2, t = 10 s, Partial discharge < 5 pC |
1697 | VPK |
Method a, After environmental tests subgroup 1, VPR = VIORM x 1.6, t = 10 s, Partial Discharge < 5 pC |
2262 | |||
Method b1, VPR = VIORM x 1.875, t = 1 s (100% Production test) Partial discharge < 5 pC |
2651 | |||
VIOTM | Maximum transient overvoltage per DIN V VDE V 0884-10 |
VTEST = VIOTM
t = 60 sec (qualification) t= 1 sec (100% production) |
4242 | VPK |
VIOSM | Maximum surge isolation voltage per DIN V VDE V 0884-10 |
Test method per IEC 60065, 1.2/50 µs waveform, VTEST = 1.3 x VIOSM = 7800 VPK (qualification) |
6000 | VPK |
VISO | Withstand isolation voltage per UL 1577 | VTEST = VISO = 3000 VRMS, t = 60 sec (qualification) VTEST = 1.2 x VISO = 3600 VRMS, t = 1 sec (100% production) |
3000 | VRMS |
RS | Insulation resistance | VIO = 500 V at TS | >109 | Ω |
Pollution degree | 2 |
PARAMETER | TEST CONDITIONS | SPECIFICATION |
---|---|---|
Basic isolation group | Material group | II |
Installation classification | Rated mains voltage ≤ 300 VRMS | I–IV |
Rated mains voltage ≤ 600 VRMS | I–III | |
Rated mains voltage ≤ 1000 VRMS | I–II |
VDE | CSA | UL | CQC |
---|---|---|---|
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN 61010-1 (VDE 0411-1):2011-07 | Approved under CSA Component Acceptance Notice 5A, IEC 60950-1, and IEC 61010-1 | Recognized under UL 1577 Component Recognition Program | Certified according to GB4943.1-2011 |
Basic Insulation Maximum Transient Overvoltage, 4242 VPK ; Maximum Surge Isolation Voltage, 6000 VPK; Maximum Repetitive Peak Isolation Voltage', 1414 VPK |
800 VRMS Basic Insulation and 400 VRMS Reinforced Insulation working voltage per CSA 60950-1-07+A1+A2 and IEC 60950-1 2nd Ed.+A1+A2; 300 VRMS Basic Insulation working voltage per CSA 61010-1-12 and IEC 61010-1 3rd Ed. |
Single protection, 3000 VRMS(1) | Reinforced Insulation, Altitude ≤ 5000 m, Tropical Climate, 250 VRMS maximum working voltage |
Certificate number: 40016131 | Master contract number: 220991 | File number: E181974 | Certificate number: CQC15001121716 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
IS | Safety input, output, or supply current | RθJA = 78.3 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C | 290 | mA | ||
RθJA = 78.3 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C | 443 | |||||
TS | Maximum case temperature | 150 | °C |
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolut Maximun Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a High-K Test Board for Leaded Surface-Mount Packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.
VCCI | VCCO | INPUT (INx) |
OUTPUT ENABLE (ENx) |
OUTPUT (OUTx) |
|
---|---|---|---|---|---|
ISO733xC | ISO733xFC | ||||
PU | PU | H | H or Open | H | H |
L | H or Open | L | L | ||
X | L | Z | Z | ||
Open | H or Open | H(2) | L(3) | ||
PD | PU | X | H or Open | H(2) | L(3) |
X | PU | X | L | Z | Z |
X | PD | X | X | Undetermined | Undetermined |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
ISO733x utilize single-ended TTL-logic switching technology. Its supply voltage range is from 3 V to 5.5 V for both supplies, VCC1 and VCC2. When designing with digital isolators, it is important to keep in mind that due to the single-ended design structure, digital isolators do not conform to any specific interface standard and are only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the data controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the interface type or standard.
ISO7331C combined with Texas Instruments' mixed signal micro-controller, RS-485 transceiver, transformer driver, and voltage regulator can create an isolated RS-485 system as shown in Figure 18.
ISO7330: | ISO7331: | ||
At VCC1 = VCC2 = 5 V
|
At VCC1 = VCC2 = 5 V
|
||
At VCC1 = VCC2 = 3.3 V
|
At VCC1 = VCC2 = 3.3 V
|
ICC1 and ICC2 are typical supply currents measured in mA, f is data rate measured in Mbps, CL is the capacitive load measured in pF.
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge (ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level performance and reliability depends, to a large extent, on the application board design and layout, the ISO733x incorporate many chip-level design improvements for overall system robustness. Some of these improvements include:
Typical eye diagrams of ISO733x below indicate low jitter and wide open eye at the maximum data rate of 25 Mbps.
Unlike Optocouplers, which need external components to improve performance, provide bias, or limit current, ISO733x only needs two external bypass capacitors to operate.