ISO7420FCC provides galvanic isolation up to 2500 VRMS for 1 minute per UL and 4242 VPK per VDE. This device has two isolated channels. Each channel has a logic input and output buffer separated by a silicon dioxide (SiO2) insulation barrier. Used in conjunction with isolated power supplies, this device prevents noise currents on a data bus or other circuit from entering the local ground and interfering with or damaging sensitive circuitry. The suffix F indicates low-output option in fail-safe conditions (see Table 2). This device has integrated noise filter for harsh environments where short noise pulses may be present at the device input pins.
ISO7420FCC has TTL input thresholds and operates from 2.7-V to 5.5-V supplies. All inputs are 5-V tolerant when supplied from a 2.7-V or 3.3-V supply.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ISO7420FCC | SOIC (8) | 4.90 mm × 3.91 mm |
Changes from B Revision (January 2014) to C Revision
Changes from A Revision (July 2013) to B Revision
Changes from * Revision (June 2013) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
GND1 | 4 | – | Ground connection for VCC1 |
GND2 | 5 | – | Ground connection for VCC2 |
INA | 2 | I | Input, channel A |
INB | 3 | I | Input, channel B |
OUTA | 7 | O | Output, channel A |
OUTB | 6 | O | Output, channel B |
VCC1 | 1 | – | Power supply, VCC1 |
VCC2 | 8 | – | Power supply, VCC2 |
MIN | MAX | UNIT | |||||
---|---|---|---|---|---|---|---|
VCC1, VCC2 | Supply voltage(2) | –0.5 | 6 | V | |||
VIO | Voltage at INx, OUTx | –0.5 | VCC + 0.5(3) | V | |||
IO | Output current | –15 | 15 | mA | |||
TJ(Max) | Maximum junction temperature | 150 | °C | ||||
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±4000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VCC1, VCC2 | Supply voltage | 2.7 | 5.5 | V | ||
IOH | High-level output current (VCC ≥ 3 V) | –4 | mA | |||
High-level output current (VCC < 3 V) | -2 | mA | ||||
IOL | Low-level output current | 4 | mA | |||
VIH | High-level input voltage | 2 | 5.5 | V | ||
VIL | Low-level input voltage | 0 | 0.8 | V | ||
tui | Input pulse duration | ≥ 4.5-V Operation | 20 | ns | ||
< 4.5-V Operation | 25 | |||||
1 / tui | Signaling rate | ≥ 4.5-V Operation | 0 | 50 | Mbps | |
< 4.5-V Operation | 0 | 40 | ||||
TJ(1) | Junction temperature | –40 | 136 | °C | ||
TA | Ambient temperature | -40 | 25 | 125 | °C |
THERMAL METRIC(1) | ISO7420FCC | UNIT | ||
---|---|---|---|---|
D (SOIC) | ||||
8 PINS | ||||
RθJA | Junction-to-ambient thermal resistance | 115.1 | °C/W | |
RθJC(top) | Junction-to-case (top) thermal resistance | 60.1 | °C/W | |
RθJB | Junction-to-board thermal resistance | 56.4 | °C/W | |
ψJT | Junction-to-top characterization parameter | 17.2 | °C/W | |
ψJB | Junction-to-board characterization parameter | 55.8 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH = –4 mA; see Figure 12. | VCC2 – 0.5 | 4.8 | V | ||
IOH = –20 μA; see Figure 12. | VCC2 – 0.1 | 5 | |||||
VOL | Low-level output voltage | IOL = 4 mA; see Figure 12. | 0.2 | 0.4 | V | ||
IOL = 20 μA; see Figure 12. | 0 | 0.1 | |||||
VI(HYS) | Input threshold voltage hysteresis | 450 | mV | ||||
IIH | High-level input current | INx = VCC1 | 10 | μA | |||
IIL | Low-level input current | INx = 0 V | –10 | μA | |||
CMTI | Common-mode transient immunity | VI = VCC1 or 0 V; see Figure 14. | 25 | 60 | kV/μs | ||
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC ICC MEASUREMENT) | |||||||
ICC1 | Supply current for VCC1 and VCC2 | DC to 1 Mbps | DC Input: VI = VCC1 or 0 V, AC Input: CL = 15pF |
0.5 | 1.1 | mA | |
ICC2 | 3 | 4.6 | |||||
ICC1 | 10 Mbps | CL = 15pF | 1 | 1.5 | |||
ICC2 | 4 | 6 | |||||
ICC1 | 25 Mbps | 1.7 | 2.5 | ||||
ICC2 | 6 | 8.5 | |||||
ICC1 | 50 Mbps | 2.7 | 4 | ||||
ICC2 | 8.5 | 12 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH = –4 mA; see Figure 12. | VCC2 – 0.5 | 3 | V | ||
IOH = –20 μA; see Figure 12. | VCC2 – 0.1 | 3.3 | |||||
VOL | Low-level output voltage | IOL = 4 mA; see Figure 12. | 0.2 | 0.4 | V | ||
IOL = 20 μA; see Figure 12. | 0 | 0.1 | |||||
VI(HYS) | Input threshold voltage hysteresis | 425 | mV | ||||
IIH | High-level input current | INx = VCC1 | 10 | μA | |||
IIL | Low-level input curre | INx = 0 V | -10 | μA | |||
CMTI | Common-mode transient immunity | VI = VCC1 or 0 V; see Figure 14. | 25 | 40 | kV/μs | ||
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC ICC MEASUREMENT) | |||||||
ICC1 | Supply current for VCC1 and VCC2 | DC to 1 Mbps | DC Input: VI = VCC1 or 0 V, AC Input: CL = 15pF |
0.3 | 0.8 | mA | |
ICC2 | 2.4 | 3.3 | |||||
ICC1 | 10 Mbps | CL = 15pF | 0.6 | 1.2 | |||
ICC2 | 3.1 | 4.5 | |||||
ICC1 | 25 Mbps | 1 | 2 | ||||
ICC2 | 4.2 | 6.1 | |||||
ICC1 | 40 Mbps | 1.3 | 2.3 | ||||
ICC2 | 5.3 | 7.5 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH = –2 mA; see Figure 12. | VCC2 – 0.3 | 2.5 | V | ||
IOH = –20 μA; see Figure 12. | VCC2 – 0.1 | 2.7 | |||||
VOL | Low-level output voltage | IOL = 4 mA; see Figure 12. | 0.2 | 0.4 | V | ||
IOL = 20 μA; see Figure 12. | 0 | 0.1 | |||||
VI(HYS) | Input threshold voltage hysteresis | 350 | mV | ||||
IIH | High-level input current | INx = VCC1 | 10 | μA | |||
IIL | Low-level input current | INx = 0 V | –10 | μA | |||
CMTI | Common-mode transient immunity | VI = VCC1 or 0 V; see Figure 14. | 25 | 35 | kV/μs | ||
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC ICC MEASUREMENT) | |||||||
ICC1 | Supply current for VCC1 and VCC2 | DC to 1 Mbps | DC Input: VI = VCC1 or 0 V, AC Input: CL = 15pF |
0.15 | 0.4 | mA | |
ICC2 | 2.1 | 3.1 | |||||
ICC1 | 10 Mbps | CL = 15pF | 0.4 | 0.7 | |||
ICC2 | 2.7 | 4 | |||||
ICC1 | 25 Mbps | 0.7 | 1.2 | ||||
ICC2 | 3.6 | 5 | |||||
ICC1 | 40 Mbps | 1 | 1.7 | ||||
ICC2 | 4.4 | 6.3 |
THERMAL METRIC | ISO7420FCC | UNIT | ||
---|---|---|---|---|
D (SOIC) | ||||
8 PINS | ||||
PD | Device power dissipation | VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 50-Mbps 50% duty-cycle square wave |
120 | mW |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tPLH, tPHL | Propagation delay time | See Figure 12. | 10 | 20 | 37 | ns |
PWD(1) | Pulse width distortion |tPHL – tPLH| | 2.5 | 5 | ns | ||
tsk(o)(2) | Channel-to-channel output skew time | 2 | ns | |||
tsk(pp)(3) | Part-to-part skew time | 12 | ns | |||
tr | Output signal rise time | See Figure 12. | 2.5 | ns | ||
tf | Output signal fall time | 2.5 | ns | |||
tGS | Pulse width of glitches suppressed by the input filter | 12 | ns | |||
tfs | Fail-safe output delay time from input data or power loss | See Figure 13. | 8 | μs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tPLH, tPHL | Propagation delay time | See Figure 12. | 10 | 22 | 40 | ns |
PWD(1) | Pulse width distortion |tPHL – tPLH| | 3 | ns | |||
tsk(o)(2) | Channel-to-channel output skew time | 2 | ns | |||
tsk(pp)(3) | Part-to-part skew time | 19 | ns | |||
tr | Output signal rise time | See Figure 12. | 3 | ns | ||
tf | Output signal fall time | 3 | ns | |||
tGS | Pulse width of glithes suppressed by the input filter | 12.5 | ns | |||
tfs | Fail-safe output delay time from input power loss | See Figure 13. | 8 | μs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tPLH, tPHL | Propagation delay time | See Figure 12. | 15 | 26 | 45 | ns |
PWD(1) | Pulse width distortion |tPHL – tPLH| | 3 | ns | |||
tsk(o)(2) | Channel-to-channel output skew time | 2 | ns | |||
tsk(pp)(3) | Part-to-part skew time | 22 | ns | |||
tr | Output signal rise time | See Figure 12. | 3 | ns | ||
tf | Output signal fall time | 3 | ns | |||
tGS | Pulse width of glitches suppressed by the input filter | 13.5 | ns | |||
tfs | Fail-safe output delay time from input power loss | See Figure 13. | 8 | μs |
The isolator in Figure 15 is based on a capacitive isolation barrier technique. The I/O channel of the device consists of two internal data channels, a high-frequency channel (HF) with a bandwidth from 100 kbps up to
50 Mbps, and a low-frequency channel (LF) covering the range from 100 kbps down to DC. In principle, a single- ended input signal entering the HF-channel is split into a differential signal via the inverter gate at the input. The following capacitor-resistor networks differentiate the signal into transients, which then are converted into differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop whose output feeds an output multiplexer. A decision logic (DCL) at the driving output of the flip-flop measures the durations between signal transients. If the duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency signal), the DCL forces the output-multiplexer to switch from the high- to the low-frequency channel.
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a sufficiently high frequency signal, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output multiplexer.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
L(I01) | Minimum air gap (clearance) | Shortest terminal-to-terminal distance through air | 4 | mm | |||
L(I02) | Minimum external tracking (creepage) | Shortest terminal-to-terminal distance across the package surface | 4 | mm | |||
CTI | Tracking resistance (comparative tracking index) | DIN EN 60112 (VDE 0303-11); IEC 60112 | >400 | V | |||
DTI | Distance through the insulation | Minimum internal gap (internal clearance) | 0.014 | mm | |||
RIO | Isolation resistance, input to output(1) | VIO = 500 V, TA = 25°C | >1012 | Ω | |||
VIO = 500 V, 100°C ≤ TA ≤ 125°C | >1011 | Ω | |||||
CIO | Barrier capacitance, input to output(1) | VIO = 0.4 sin (2πft), f = 1 MHz | 1 | pF | |||
CI | Input capacitance(2) | VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V | 1 | pF |
NOTE
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance.
Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
PARAMETER | TEST CONDITIONS | SPECIFICATION | UNIT | |
---|---|---|---|---|
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12(1) | ||||
VIORM | Maximum working isolation voltage | 566 | VPK | |
VPR | Input-to-output test voltage | Method a, After environmental tests subgroup 1, VPR = VIORM x 1.6, t = 10 s, Partial Discharge < 5 pC |
906 | VPK |
Method b1, VPR = VIORM x 1.875, t = 1 s (100% Production test) Partial discharge < 5 pC |
1062 | |||
After Input/Output safety test subgroup 2/3, VPR = VIORM x 1.2, t = 10 s, Partial discharge < 5 pC |
680 | |||
VIOTM | Maximum transient isolation voltage | VTEST = VIOTM
t = 60 sec (qualification) t= 1 sec (100% production) |
4242 | VPK |
RS | Isolation resistance | VIO = 500 V at TS = 150°C | >109 | Ω |
Pollution degree | 2 | |||
UL 1577 | ||||
VISO | Isolation voltage | VTEST = VISO = 2500 VRMS, t = 60 sec (qualification) VTEST = 1.2 x VISO= 3000 VRMS, t = 1 sec (100% production) |
2500 | VRMS |
PARAMETER | TEST CONDITIONS | SPECIFICATION |
---|---|---|
Material group | II | |
Installation classification | Rated mains voltage ≤ 150 VRMS | I–IV |
Rated mains voltage ≤ 300 VRMS | I–III |
VDE | CSA | UL | CQC |
---|---|---|---|
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN 61010-1 (VDE 0411-1):2011-07 | Approved under CSA Component Acceptance Notice 5A, IEC 60950-1, and IEC 61010-1 | Recognized under UL 1577 Component Recognition Program | Certified according to GB4943.1-2011 |
Basic Insulation Maximum Transient Isolation voltage, 4242 VPK; Maximum Working Isolation Voltage, 566 VPK |
3000 VRMS Isolation Rating; 400 VRMS Basic and 200 VRMS Reinforced Insulation maximum working voltage per CSA 60950-1-07+A1 and IEC 60950-1 (2nd Ed)+A1; 300 VRMS Basic and 150 VRMS Reinforced Insulation maximum working voltage per CSA 61010-1-12 and IEC 61010-1 (3rd Ed) |
Single Protection, 2500 VRMS(1) | Basic Insulation, Altitude ≤ 5000m, Tropical Climate, 250 VRMS maximum working voltage |
Certificate number: 40016131 | Master contract number: 220991 | File number: E181974 | Certificate number: CQC14001109540 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
IS | Safety input, output, or supply current | θJA = 115.1°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C | 197 | mA | ||
θJA = 115.1°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C | 302 | |||||
θJA = 115.1°C/W, VI = 2.7 V, TJ = 150°C, TA = 25°C | 402 | |||||
TS | Maximum Safety temperature | 150 | °C |
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a High-K Test Board for Leaded Surface-Mount Packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.
VCC1 | VCC2 | INPUT INA, INB |
OUTPUT OUTA, OUTB |
---|---|---|---|
PU | PU | H | H |
L | L | ||
Open | L(2) | ||
PD | PU | X | L(2) |
X | PD | X | Undetermined |