ISO7420FCC provides galvanic isolation up to 2500 VRMS for 1 minute per UL and 4242 VPK per VDE. This device has two isolated channels. Each channel has a logic input and output buffer separated by a silicon dioxide (SiO2) insulation barrier. Used in conjunction with isolated power supplies, this device prevents noise currents on a data bus or other circuit from entering the local ground and interfering with or damaging sensitive circuitry. The suffix F indicates low-output option in fail-safe conditions (see Table 2). This device has integrated noise filter for harsh environments where short noise pulses may be present at the device input pins.
ISO7420FCC has TTL input thresholds and operates from 2.7-V to 5.5-V supplies. All inputs are 5-V tolerant when supplied from a 2.7-V or 3.3-V supply.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ISO7420FCC | SOIC (8) | 4.90 mm × 3.91 mm |
Changes from B Revision (January 2014) to C Revision
Changes from A Revision (July 2013) to B Revision
Changes from * Revision (June 2013) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
GND1 | 4 | – | Ground connection for VCC1 |
GND2 | 5 | – | Ground connection for VCC2 |
INA | 2 | I | Input, channel A |
INB | 3 | I | Input, channel B |
OUTA | 7 | O | Output, channel A |
OUTB | 6 | O | Output, channel B |
VCC1 | 1 | – | Power supply, VCC1 |
VCC2 | 8 | – | Power supply, VCC2 |
MIN | MAX | UNIT | |||||
---|---|---|---|---|---|---|---|
VCC1, VCC2 | Supply voltage(2) | –0.5 | 6 | V | |||
VIO | Voltage at INx, OUTx | –0.5 | VCC + 0.5(3) | V | |||
IO | Output current | –15 | 15 | mA | |||
TJ(Max) | Maximum junction temperature | 150 | °C | ||||
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±4000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VCC1, VCC2 | Supply voltage | 2.7 | 5.5 | V | ||
IOH | High-level output current (VCC ≥ 3 V) | –4 | mA | |||
High-level output current (VCC < 3 V) | -2 | mA | ||||
IOL | Low-level output current | 4 | mA | |||
VIH | High-level input voltage | 2 | 5.5 | V | ||
VIL | Low-level input voltage | 0 | 0.8 | V | ||
tui | Input pulse duration | ≥ 4.5-V Operation | 20 | ns | ||
< 4.5-V Operation | 25 | |||||
1 / tui | Signaling rate | ≥ 4.5-V Operation | 0 | 50 | Mbps | |
< 4.5-V Operation | 0 | 40 | ||||
TJ(1) | Junction temperature | –40 | 136 | °C | ||
TA | Ambient temperature | -40 | 25 | 125 | °C |
THERMAL METRIC(1) | ISO7420FCC | UNIT | ||
---|---|---|---|---|
D (SOIC) | ||||
8 PINS | ||||
RθJA | Junction-to-ambient thermal resistance | 115.1 | °C/W | |
RθJC(top) | Junction-to-case (top) thermal resistance | 60.1 | °C/W | |
RθJB | Junction-to-board thermal resistance | 56.4 | °C/W | |
ψJT | Junction-to-top characterization parameter | 17.2 | °C/W | |
ψJB | Junction-to-board characterization parameter | 55.8 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH = –4 mA; see Figure 12. | VCC2 – 0.5 | 4.8 | V | ||
IOH = –20 μA; see Figure 12. | VCC2 – 0.1 | 5 | |||||
VOL | Low-level output voltage | IOL = 4 mA; see Figure 12. | 0.2 | 0.4 | V | ||
IOL = 20 μA; see Figure 12. | 0 | 0.1 | |||||
VI(HYS) | Input threshold voltage hysteresis | 450 | mV | ||||
IIH | High-level input current | INx = VCC1 | 10 | μA | |||
IIL | Low-level input current | INx = 0 V | –10 | μA | |||
CMTI | Common-mode transient immunity | VI = VCC1 or 0 V; see Figure 14. | 25 | 60 | kV/μs | ||
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC ICC MEASUREMENT) | |||||||
ICC1 | Supply current for VCC1 and VCC2 | DC to 1 Mbps | DC Input: VI = VCC1 or 0 V, AC Input: CL = 15pF |
0.5 | 1.1 | mA | |
ICC2 | 3 | 4.6 | |||||
ICC1 | 10 Mbps | CL = 15pF | 1 | 1.5 | |||
ICC2 | 4 | 6 | |||||
ICC1 | 25 Mbps | 1.7 | 2.5 | ||||
ICC2 | 6 | 8.5 | |||||
ICC1 | 50 Mbps | 2.7 | 4 | ||||
ICC2 | 8.5 | 12 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH = –4 mA; see Figure 12. | VCC2 – 0.5 | 3 | V | ||
IOH = –20 μA; see Figure 12. | VCC2 – 0.1 | 3.3 | |||||
VOL | Low-level output voltage | IOL = 4 mA; see Figure 12. | 0.2 | 0.4 | V | ||
IOL = 20 μA; see Figure 12. | 0 | 0.1 | |||||
VI(HYS) | Input threshold voltage hysteresis | 425 | mV | ||||
IIH | High-level input current | INx = VCC1 | 10 | μA | |||
IIL | Low-level input curre | INx = 0 V | -10 | μA | |||
CMTI | Common-mode transient immunity | VI = VCC1 or 0 V; see Figure 14. | 25 | 40 | kV/μs | ||
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC ICC MEASUREMENT) | |||||||
ICC1 | Supply current for VCC1 and VCC2 | DC to 1 Mbps | DC Input: VI = VCC1 or 0 V, AC Input: CL = 15pF |
0.3 | 0.8 | mA | |
ICC2 | 2.4 | 3.3 | |||||
ICC1 | 10 Mbps | CL = 15pF | 0.6 | 1.2 | |||
ICC2 | 3.1 | 4.5 | |||||
ICC1 | 25 Mbps | 1 | 2 | ||||
ICC2 | 4.2 | 6.1 | |||||
ICC1 | 40 Mbps | 1.3 | 2.3 | ||||
ICC2 | 5.3 | 7.5 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOH | High-level output voltage | IOH = –2 mA; see Figure 12. | VCC2 – 0.3 | 2.5 | V | ||
IOH = –20 μA; see Figure 12. | VCC2 – 0.1 | 2.7 | |||||
VOL | Low-level output voltage | IOL = 4 mA; see Figure 12. | 0.2 | 0.4 | V | ||
IOL = 20 μA; see Figure 12. | 0 | 0.1 | |||||
VI(HYS) | Input threshold voltage hysteresis | 350 | mV | ||||
IIH | High-level input current | INx = VCC1 | 10 | μA | |||
IIL | Low-level input current | INx = 0 V | –10 | μA | |||
CMTI | Common-mode transient immunity | VI = VCC1 or 0 V; see Figure 14. | 25 | 35 | kV/μs | ||
SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE WAVE CLOCK SIGNAL FOR DYNAMIC ICC MEASUREMENT) | |||||||
ICC1 | Supply current for VCC1 and VCC2 | DC to 1 Mbps | DC Input: VI = VCC1 or 0 V, AC Input: CL = 15pF |
0.15 | 0.4 | mA | |
ICC2 | 2.1 | 3.1 | |||||
ICC1 | 10 Mbps | CL = 15pF | 0.4 | 0.7 | |||
ICC2 | 2.7 | 4 | |||||
ICC1 | 25 Mbps | 0.7 | 1.2 | ||||
ICC2 | 3.6 | 5 | |||||
ICC1 | 40 Mbps | 1 | 1.7 | ||||
ICC2 | 4.4 | 6.3 |
THERMAL METRIC | ISO7420FCC | UNIT | ||
---|---|---|---|---|
D (SOIC) | ||||
8 PINS | ||||
PD | Device power dissipation | VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 50-Mbps 50% duty-cycle square wave |
120 | mW |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tPLH, tPHL | Propagation delay time | See Figure 12. | 10 | 20 | 37 | ns |
PWD(1) | Pulse width distortion |tPHL – tPLH| | 2.5 | 5 | ns | ||
tsk(o)(2) | Channel-to-channel output skew time | 2 | ns | |||
tsk(pp)(3) | Part-to-part skew time | 12 | ns | |||
tr | Output signal rise time | See Figure 12. | 2.5 | ns | ||
tf | Output signal fall time | 2.5 | ns | |||
tGS | Pulse width of glitches suppressed by the input filter | 12 | ns | |||
tfs | Fail-safe output delay time from input data or power loss | See Figure 13. | 8 | μs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tPLH, tPHL | Propagation delay time | See Figure 12. | 10 | 22 | 40 | ns |
PWD(1) | Pulse width distortion |tPHL – tPLH| | 3 | ns | |||
tsk(o)(2) | Channel-to-channel output skew time | 2 | ns | |||
tsk(pp)(3) | Part-to-part skew time | 19 | ns | |||
tr | Output signal rise time | See Figure 12. | 3 | ns | ||
tf | Output signal fall time | 3 | ns | |||
tGS | Pulse width of glithes suppressed by the input filter | 12.5 | ns | |||
tfs | Fail-safe output delay time from input power loss | See Figure 13. | 8 | μs |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tPLH, tPHL | Propagation delay time | See Figure 12. | 15 | 26 | 45 | ns |
PWD(1) | Pulse width distortion |tPHL – tPLH| | 3 | ns | |||
tsk(o)(2) | Channel-to-channel output skew time | 2 | ns | |||
tsk(pp)(3) | Part-to-part skew time | 22 | ns | |||
tr | Output signal rise time | See Figure 12. | 3 | ns | ||
tf | Output signal fall time | 3 | ns | |||
tGS | Pulse width of glitches suppressed by the input filter | 13.5 | ns | |||
tfs | Fail-safe output delay time from input power loss | See Figure 13. | 8 | μs |