11.1 Layout Guidelines

There are several signals that conduct fast charging current or voltages that can interact with stray inductance or parasitic capacitors to generate noise. Thus to eliminate these problems Vin ins of ISO7421 should be bypass to gnd with low esr ceramic bypass capacitor with X7R dielectric. A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 15). Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer.

• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100pF/in².
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias.

If an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly.

For detailed layout recommendations, see Application Note Digital Isolator Design Guide, SLLA284.

11.2 Layout Example

Figure 15. Recommended Layer Stack