SLLSE89G September   2011  – January 2015 ISO7640FM , ISO7641FM

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: VCC1 and VCC2 at 5 V ±10%
    6. 6.6  Electrical Characteristics: VCC1 at 5 V ±10% and VCC2 at 3.3 V ±10%
    7. 6.7  Electrical Characteristics: VCC1 at 3.3 V ±10% and VCC2 at 5 V ±10%
    8. 6.8  Electrical Characteristics: VCC1 and VCC2 at 3.3 V ±10%
    9. 6.9  Electrical Characteristics: VCC1 and VCC2 at 2.7 V
    10. 6.10 Supply Current: VCC1 and VCC2 at 5 V ±10%
    11. 6.11 Supply Current: VCC1 at 5 V ±10% and VCC2 at 3.3 V ±10%
    12. 6.12 Supply Current: VCC1 at 3.3 V ±10% and VCC2 at 5 V ±10%
    13. 6.13 Supply Current: VCC1 and VCC2 at 3.3 V ±10%
    14. 6.14 Supply Current: VCC1 and VCC2 at 2.7 V
    15. 6.15 Switching Characteristics: VCC1 and VCC2 at 5 V ±10%
    16. 6.16 Switching Characteristics: VCC1 at 5 V ±10% and VCC2 at 3.3 V ±10%
    17. 6.17 Switching Characteristics: VCC1 at 3.3 V ±10% and VCC2 at 5 V ±10%
    18. 6.18 Switching Characteristics: VCC1 and VCC2 at 3.3 V ±10%
    19. 6.19 Switching Characteristics: VCC1 and VCC2 at 2.7 V
    20. 6.20 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 IEC Insulation and Safety-Related Specifications for DW-16 Package
      2. 8.3.2 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics
      3. 8.3.3 Safety Limiting Values
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Typical Supply Current Equations
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings(1)

MIN MAX UNIT
Supply voltage(2) VCC1, VCC2 –0.5 6 V
Voltage INx, OUTx, ENx –0.5 VCC + 0.5(3) V
Output Current, IO –15 15 mA
Maximum junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak voltage values.
(3) Maximum voltage must not exceed 6 V.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±4000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1500
Machine model, per JEDEC JESD22-A115-A ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC1, VCC2 Supply voltage 2.7 5.5 V
IOH High-level output current –4 mA
IOL Low-level output current 4 mA
VIH High-level input voltage 2 5.5 V
VIL Low-level input voltage 0 0.8 V
tui Input pulse duration ≥3-V Operation 6.67 ns
<3-V Operation 10
1 / tui Signaling rate ≥3-V Operation 0 150 Mbps
<3-V Operation 0 100
TJ Junction temperature –40 136 °C
TA Ambient temperature –40 25 125 °C

6.4 Thermal Information

THERMAL METRIC(1) ISO76xx UNIT
DW (SOIC)
16 PINS
RθJA Junction-to-ambient thermal resistance 72 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 38
RθJB Junction-to-board thermal resistance 39
ψJT Junction-to-top characterization parameter 9.4
PD Maximum Device Power Dissipation VCC1 = VCC2 = 5.5V, TJ = 150°C, CL = 15 pF
Input a 75-MHz 50% duty cycle square wave		 399 mW
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics: VCC1 and VCC2 at 5 V ±10%

VCC1 and VCC2 at 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –4 mA; see Figure 9 VCCO(1) –0.8 4.8 V
IOH = –20 μA; see Figure 9 VCCO(1) –0.1 5
VOL Low-level output voltage IOL = 4 mA; see Figure 9 0.2 0.4 V
IOL = 20 μA; see Figure 9 0 0.1
VI(HYS) Input threshold voltage hysteresis 450 mV
IIH High-level input current VIH = VCC at INx or ENx 10 μA
IIL Low-level input current VIL = 0 V at INx or ENx –10
CMTI Common-mode transient immunity VI = VCC or 0 V; see Figure 12 25 75 kV/μs
(1) VCCO is the supply voltage, VCC1 or VCC2, for the output channel that is being measured.

6.6 Electrical Characteristics: VCC1 at 5 V ±10% and VCC2 at 3.3 V ±10%

VCC1 at 5 V ±10% and VCC2 at 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –4 mA; see Figure 9 OUTx on VCC1 (5V) side VCC1 – 0.8 4.8 V
OUTx on VCC2 (3.3V) side VCC2 – 0.4 3
IOH = –20 μA; see Figure 9 OUTx on VCC1 (5V) side VCC1 – 0.1 5
OUTx on VCC2 (3.3V) side VCC2 – 0.1 3.3
VOL Low-level output voltage IOL = 4 mA; see Figure 9 0.2 0.4 V
IOL = 20 μA; see Figure 9 0 0.1
VI(HYS) Input threshold voltage hysteresis 430 mV
IIH High-level input current VIH = VCC at INx or ENx 10 μA
IIL Low-level input current VIL = 0 V at INx or ENx –10
CMTI Common-mode transient immunity VI = VCC or 0 V; see Figure 12 25 50 kV/μs

6.7 Electrical Characteristics: VCC1 at 3.3 V ±10% and VCC2 at 5 V ±10%

VCC1 at 3.3 V ±10% and VCC2 at 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –4 mA; see Figure 9 OUTx on VCC1 (3.3 V) side VCC1–0.4 3 V
OUTx on VCC2 (5 V) side VCC2–0.8 4.8
IOH = –20 μA; see Figure 9 OUTx on VCC1 (3.3 V) side VCC1–0.1 3.3
OUTx on VCC2 (5 V) side VCC2–0.1 5
VOL Low-level output voltage IOL = 4 mA; see Figure 9 0.2 0.4 V
IOL = 20 μA; see Figure 9 0 0.1
VI(HYS) Input threshold voltage hysteresis 430 mV
IIH High-level input current VIH = VCC at INx or ENx 10 μA
IIL Low-level input current VIL = 0 V at INx or ENx –10
CMTI Common-mode transient immunity VI = VCC or 0 V; see Figure 12 25 50 kV/μs

6.8 Electrical Characteristics: VCC1 and VCC2 at 3.3 V ±10%

VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –4 mA; see Figure 9 VCCO(1) – 0.4 3 V
IOH = –20 μA; see Figure 9 VCCO(1) – 0.1 3.3
VOL Low-level output voltage IOL = 4 mA; see Figure 9 0.2 0.4 V
IOL = 20 μA; see Figure 9 0 0.1
VI(HYS) Input threshold voltage hysteresis 425 mV
IIH High-level input current VIH = VCC at INx or ENx 10 μA
IIL Low-level input current VIL = 0 V at INx or ENx –10
CMTI Common-mode transient immunity VI = VCC or 0 V; see Figure 12 25 50 kV/μs
(1) VCCO is the supply voltage, VCC1 or VCC2, for the output channel that is being measured.

6.9 Electrical Characteristics: VCC1 and VCC2 at 2.7 V

VCC1 and VCC2 at 2.7 V(1) (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –4 mA; see Figure 9 VCCO(2) – 0.5 2.4 V
IOH = –20 μA; see Figure 9 VCCO(2) – 0.1 2.7
VOL Low-level output voltage IOL = 4 mA; see Figure 9 0.2 0.4 V
IOL = 20 μA; see Figure 9 0 0.1
VI(HYS) Input threshold voltage hysteresis 350 mV
IIH High-level input current VIH = VCC at INx or ENx 10 μA
IIL Low-level input current VIL = 0 V at INx or ENx –10
CMTI Common-mode transient immunity VI = VCC or 0 V; see Figure 12 25 50 kV/μs
(1) For 2.7-V operation, max data rate is 100 Mbps.
(2) VCCO is the supply voltage, VCC1 or VCC2, for the output channel that is being measured.

6.10 Supply Current: VCC1 and VCC2 at 5 V ±10%

VCC1 and VCC2 at 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISO7640FM
ICC1 Disable EN = 0 V 0.6 1.2 mA
ICC2 4.5 6.6
ICC1 DC to 1 Mbps DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with square wave clock input; CL = 15 pF		 0.7 1.3
ICC2 4.6 6.7
ICC1 10 Mbps 1.1 2
ICC2 6.6 10.5
ICC1 25 Mbps 1.9 3
ICC2 9.7 14.7
ICC1 150 Mbps 8.2 14.5
ICC2 35 58
ISO7641FM
ICC1 Disable EN1 = EN2 = 0 V 2.6 4.2 mA
ICC2 4.2 6.8
ICC1 DC to 1 Mbps DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with square wave clock input; CL = 15 pF		 2.7 4.3
ICC2 4.3 6.9
ICC1 10 Mbps 3.6 4.9
ICC2 6 8.2
ICC1 25 Mbps 5.1 6.6
ICC2 8.8 11.4
ICC1 150 Mbps 17 22
ICC2 31 42

6.11 Supply Current: VCC1 at 5 V ±10% and VCC2 at 3.3 V ±10%

VCC1 at 5 V ±10% and VCC2 at 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISO7640FM
ICC1 Disable EN = 0 V 0.6 1.2 mA
ICC2 3.6 5.1
ICC1 DC to 1 Mbps DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with square wave clock input; CL = 15 pF		 0.7 1.3
ICC2 3.7 5.2
ICC1 10 Mbps 1.1 2
ICC2 5 7.1
ICC1 25 Mbps 1.9 3
ICC2 6.9 11
ICC1 150 Mbps 8.2 14.5
ICC2 24 40
ISO7641FM
ICC1 Disable EN1 = EN2 = 0 V 2.6 4.2 mA
ICC2 3.2 4.9
ICC1 DC to 1 Mbps DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with square wave clock input; CL = 15 pF		 2.7 4.3
ICC2 3.3 5
ICC1 10 Mbps 3.6 4.9
ICC2 4.4 5.8
ICC1 25 Mbps 5.1 6.6
ICC2 6.1 7.6
ICC1 150 Mbps 17 22
ICC2 20.6 26.5

6.12 Supply Current: VCC1 at 3.3 V ±10% and VCC2 at 5 V ±10%

VCC1 at 3.3 V ±10% and VCC2 at 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISO7640FM
ICC1 Disable EN = 0 V 0.35 0.7 mA
ICC2 4.5 6.6
ICC1 DC to 1 Mbps DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with square wave clock input; CL = 15 pF		 0.4 0.8
ICC2 4.6 6.7
ICC1 10 Mbps 0.7 1.2
ICC2 6.6 10.5
ICC1 25 Mbps 1.1 2
ICC2 9.7 14.7
ICC1 150 Mbps 5 8.5
ICC2 35 58
ISO7641FM
ICC1 Disable EN1 = EN2 = 0 V 1.9 2.9 mA
ICC2 4.2 6.8
ICC1 DC to 1 Mbps DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with square wave clock input; CL = 15 pF		 2 3
ICC2 4.3 6.9
ICC1 10 Mbps 2.5 3.5
ICC2 6 8.2
ICC1 25 Mbps 3.4 4.5
ICC2 8.8 11.4
ICC1 150 Mbps 10.5 14.5
ICC2 31 42

6.13 Supply Current: VCC1 and VCC2 at 3.3 V ±10%

VCC1 and VCC2 at 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISO7640FM
ICC1 Disable EN = 0 V 0.35 0.7 mA
ICC2 3.6 5.1
ICC1 DC to 1 Mbps DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with square wave clock input; CL = 15 pF		 0.4 0.8
ICC2 3.7 5.2
ICC1 10 Mbps 0.7 1.2
ICC2 5 7.1
ICC1 25 Mbps 1.1 2
ICC2 6.9 11
ICC1 150 Mbps 5 8.5
ICC2 24 40
ISO7641FM
ICC1 Disable EN1 = EN2 = 0 V 1.9 2.9 mA
ICC2 3.2 4.9
ICC1 DC to 1 Mbps DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with square wave clock input; CL = 15 pF		 2 3
ICC2 3.3 5
ICC1 10 Mbps 2.5 3.5
ICC2 4.4 5.8
ICC1 25 Mbps 3.4 4.5
ICC2 6.1 7.6
ICC1 150 Mbps 10.5 14.5
ICC2 20.6 26.5

6.14 Supply Current: VCC1 and VCC2 at 2.7 V

VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISO7640FM
ICC1 Disable EN = 0 V 0.2 0.6 mA
ICC2 3.3 5
ICC1 DC to 1 Mbps DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with square wave clock input; CL = 15 pF		 0.2 0.7
ICC2 3.4 5.1
ICC1 10 Mbps 0.4 1.1
ICC2 4.4 6.8
ICC1 25 Mbps 0.8 1.8
ICC2 6 9.5
ICC1 100 Mbps 2.7 5
ICC2 14.2 21
ISO7641FM
ICC1 Disable EN1 = EN2 = 0 V 1.6 2.4 mA
ICC2 2.8 4.1
ICC1 DC to 1 Mbps DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with square wave clock input; CL = 15 pF		 1.7 2.5
ICC2 2.9 4.2
ICC1 10 Mbps 2.1 3
ICC2 3.8 5
ICC1 25 Mbps 2.8 3.8
ICC2 5.2 6.7
ICC1 100 Mbps 6.4 7.5
ICC2 11.8 15.5

6.15 Switching Characteristics: VCC1 and VCC2 at 5 V ±10%

VCC1 and VCC2 at 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 9 3.5 7 10.5 ns
PWD(1) Pulse width distortion |tPHL – tPLH| 2
tsk(o)(2) Channel-to-channel output skew time Same-direction Channels 2
Opposite-direction Channels 3
tsk(pp)(3) Part-to-part skew time 4.5
tr Output signal rise time See Figure 9 1.6 ns
tf Output signal fall time 1
tPHZ Disable Propagation Delay, high-to-high impedance output See Figure 10 5 16 ns
tPLZ Disable Propagation Delay, low-to-high impedance output 5 16
tPZH Enable Propagation Delay, high impedance-to-high output 4 16
tPZL Enable Propagation Delay, high impedance-to-low output 4 16
tfs Fail-safe output delay time from input data or power loss See Figure 11 9.5 μs
(1) Also known as Pulse Skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

6.16 Switching Characteristics: VCC1 at 5 V ±10% and VCC2 at 3.3 V ±10%

VCC1 at 5 V ±10% and VCC2 at 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 9 4 8 13 ns
PWD(1) Pulse width distortion |tPHL – tPLH| 2
tsk(o)(2) Channel-to-channel output skew time Same-direction Channels 2.5
Opposite-direction Channels 3.5
tsk(pp)(3) Part-to-part skew time 6
tr Output signal rise time See Figure 9 2 ns
tf Output signal fall time 1.2
tPHZ Disable Propagation Delay, high-to-high impedance output See Figure 10 6.5 17 ns
tPLZ Disable Propagation Delay, low-to-high impedance output 6.5 17
tPZH Enable Propagation Delay, high impedance-to-high output 5.5 17
tPZL Enable Propagation Delay, high impedance-to-low output 5.5 17
tfs Fail-safe output delay time from input data or power loss See Figure 11 9.5 μs
(1) Also known as Pulse Skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

6.17 Switching Characteristics: VCC1 at 3.3 V ±10% and VCC2 at 5 V ±10%

VCC1 at 3.3 V ±10% and VCC2 at 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 9 4 7.5 12.5 ns
PWD(1) Pulse width distortion |tPHL – tPLH| 2
tsk(o)(2) Channel-to-channel output skew time Same-direction Channels 2.5
Opposite-direction Channels 3.5
tsk(pp)(3) Part-to-part skew time 6
tr Output signal rise time See Figure 9 1.7 ns
tf Output signal fall time 1.1
tPHZ Disable Propagation Delay, high-to-high impedance output See Figure 10 5.5 17 ns
tPLZ Disable Propagation Delay, low-to-high impedance output 5.5 17
tPZH Enable Propagation Delay, high impedance-to-high output 4.5 17
tPZL Enable Propagation Delay, high impedance-to-low output 4.5 17
tfs Fail-safe output delay time from input data or power loss See Figure 11 9.5 μs
(1) Also known as Pulse Skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

6.18 Switching Characteristics: VCC1 and VCC2 at 3.3 V ±10%

VCC1 and VCC2 at 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 9 4 8.5 14 ns
PWD(1) Pulse width distortion |tPHL – tPLH| 2
tsk(o)(2) Channel-to-channel output skew time Same-direction Channels 3
Opposite-direction Channels 4
tsk(pp)(3) Part-to-part skew time 6.5
tr Output signal rise time See Figure 9 2 ns
tf Output signal fall time 1.3
tPHZ Disable Propagation Delay, high-to-high impedance output See Figure 10 6.5 17 ns
tPLZ Disable Propagation Delay, low-to-high impedance output 6.5 17
tPZH Enable Propagation Delay, high impedance-to-high output 5.5 17
tPZL Enable Propagation Delay, high impedance-to-low output 5.5 17
tfs Fail-safe output delay time from input data or power loss See Figure 11 9.2 μs
(1) Also known as Pulse Skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

6.19 Switching Characteristics: VCC1 and VCC2 at 2.7 V

VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 9 5 8 16 ns
PWD(1) Pulse width distortion |tPHL – tPLH| 2.5
tsk(o)(2) Channel-to-channel output skew time Same-direction Channels 4
Opposite-direction Channels 5
tsk(pp)(3) Part-to-part skew time 8
tr Output signal rise time See Figure 9 2.3 ns
tf Output signal fall time 1.8
tPHZ Disable Propagation Delay, high-to-high impedance output See Figure 10 8 18 ns
tPLZ Disable Propagation Delay, low-to-high impedance output 8 18
tPZH Enable Propagation Delay, high impedance-to-high output 7 18
tPZL Enable Propagation Delay, high impedance-to-low output 7 18
tfs Fail-safe output delay time from input data or power loss See Figure 11 8.5 μs
(1) Also known as Pulse Skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

6.20 Typical Characteristics

ISO7640FM ISO7641FM G001_SLLSE89.gifFigure 1. ISO7640FM Supply Current per Channel
vs Data Rate
ISO7640FM ISO7641FM G003_SLLSE89.gifFigure 3. ISO7641FM Supply Current per Channel
vs Data Rate
ISO7640FM ISO7641FM G006_SLLSE89.pngFigure 5. Low-Level Output Voltage
vs Low-Level Output Current
ISO7640FM ISO7641FM G008_SLLSE89.pngFigure 7. Propagation Delay Time
vs Free Air Temperature
ISO7640FM ISO7641FM G002_SLLSE89.gifFigure 2. ISO7640FM Supply Current for All Channels
vs Data Rate
ISO7640FM ISO7641FM G005_SLLSE89.pngFigure 4. High-Level Output Voltage
vs High-Level Output Current
ISO7640FM ISO7641FM G007_SLLSE89.pngFigure 6. VCC Undervoltage Threshold
vs Free Air Temperature
ISO7640FM ISO7641FM G009_SLLSE89.gifFigure 8. Output Jitter vs Data Rate