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  • ISO7830x High-Performance, 8000-VPK Reinforced Triple Digital Isolators

    • SLLSEO2B July   2015  – June 2016 ISO7830

      PRODUCTION DATA.  

  • CONTENTS
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  • ISO7830x High-Performance, 8000-VPK Reinforced Triple Digital Isolators
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Rating
    6. 6.6  Insulation Characteristics
    7. 6.7  Regulatory Information
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics—5-V Supply
    10. 6.10 Supply Current Characteristics—5-V Supply
    11. 6.11 Electrical Characteristics—3.3-V Supply
    12. 6.12 Supply Current Characteristics—3.3-V Supply
    13. 6.13 Electrical Characteristics—2.5-V Supply
    14. 6.14 Supply Current Characteristics—2.5-V Supply
    15. 6.15 Switching Characteristics—5-V Supply
    16. 6.16 Switching Characteristics—3.3-V Supply
    17. 6.17 Switching Characteristics—2.5-V Supply
    18. 6.18 Insulation Characteristics Curves
    19. 6.19 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Electromagnetic Compatibility (EMC) Considerations
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device I/O Schematics
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DWW|16
  • DW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information
  • sllseo2b_oa
  • sllseo2b_pm
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DATA SHEET

ISO7830x High-Performance, 8000-VPK Reinforced Triple Digital Isolators

1 Features

  • Signaling Rate: Up to 100 Mbps
  • Wide Supply Range: 2.25 V to 5.5 V
  • 2.25 V to 5.5 V Level Translation
  • Wide Temperature Range: –55°C to 125°C
  • Low Power Consumption, Typical 1.6 mA per Channel at 1 Mbps
  • Low Propagation Delay: 11 ns Typical
    (5-V Supplies)
  • Industry leading CMTI (min): ±100 kV/μs
  • Robust Electromagnetic Compatibility (EMC)
  • System-Level ESD, EFT, and Surge Immunity
  • Low Emissions
  • Isolation Barrier Life: > 40 Years
  • SOIC-16 Wide Body (DW) and Extra-Wide Body (DWW) Package Options
  • Safety-Related Certifications:
    • 8000 VPK Reinforced Isolation per DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
    • 5.7 kVRMS Isolation for 1 Minute per UL 1577
    • CSA Component Acceptance Notice 5A, IEC 60950-1 and IEC 60601-1 End Equipment Standards
    • CQC Certification per GB4943.1-2011
    • TUV Certification per EN 61010-1 and EN 60950-1
    • All DW Package Certifications Complete; DWW Package Certifications Complete per UL, VDE, TUV and Planned for CSA and CQC

2 Applications

  • Industrial Automation
  • Motor Control
  • Power Supplies
  • Solar Inverters
  • Medical Equipment
  • Hybrid Electric Vehicles

3 Description

The ISO7830x device is a high-performance, 3-channel digital isolator with 8000-VPK isolation voltage. This device has reinforced isolation certifications according to VDE, CSA, TUV and CQC. The isolator provides high electromagnetic immunity and low emissions at low power consumption, while isolating CMOS or LVCMOS digital I/Os.

Each isolation channel has a logic input and output buffer separated by silicon dioxide (SiO2) insulation barrier. This device comes with enable pins which can be used to put the respective outputs in high impedance for multi-master driving applications and to reduce power consumption. The ISO7830x device has three forward and no reverse-direction channels. If the input power or signal is lost, the default output is high for the ISO7830 device and low for the ISO7830F device. See Device Functional Modes for further details.

Used in conjunction with isolated power supplies, this device helps prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. Through innovative chip design and layout techniques, electromagnetic compatibility of ISO7830x has been significantly enhanced to ease system-level ESD, EFT, surge, and emissions compliance. ISO7830x is available in a 16-pin SOIC wide-body (DW) and extra-wide body (DWW) packages.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
ISO7830
ISO7830F		 DW (16) 10.30 mm × 7.50 mm
DWW (16) 10.30 mm × 14.0 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

ISO7830 ISO7830F Simplified_Schematic_sllseo2.gif
VCCI and GNDI are supply and ground connections respectively for the input channels.
VCCO and GNDO are supply and ground connections respectively for the output channels.

4 Revision History

Changes from A Revision (September 2015) to B Revision

  • Changed Features From: Low Power Consumption, Typical 2.4 mA per Channel at 1 Mbps To: Low Power Consumption, Typical 1.6 mA per Channel at 1 Mbps Go
  • Changed the isolation barrier life from > 25 years to > 40 years in the Features sectionGo
  • Changed Features From: Safety and Regulatory Approvals To: Safety-Related Certifications Go
  • Updated the status of the certifications throughout the document Go
  • Added the extra-wide body package (16 pin SOIC [DWW]) optionGo
  • Deleted EN1 from the pin out drawing in the Pin Configuration and Functions section. Replaced references of ENx with EN2Go
  • Changed pin VCC1 description From: Power supply, VCC1 To: Power supply, side 1 in the PIN Functions tableGo
  • Changed pin VCC2 description From: Power supply, VCC2 To: Power supply, side 2 in the PIN Functions tableGo
  • Moved Junction temperature From Recommended Operating Conditions To Absolute Maximum RatingsGo
  • Changed the values for the DW package in the Thermal Information table Go
  • Changed the maximum power dissipation values for side 1 (40 to 25) and side 2 (110 to 125) in the Power Rating tableGo
  • Moved Insulation Characteristics to the Specifications sectionGo
  • Changed CIO Specification From: 2 pF To: ~1 pF Go
  • Added the climatic category parameter to the Insulation Characteristics table Go
  • Moved Regulatory Information to the Specifications sectionGo
  • Moved Safety Limiting Values to the Specifications sectionGo
  • Changed the test conditions and values for the DW package in the Safety Limiting Values tableGo
  • Changed VCCO to VCCI in the minimum value for the input threshold voltage hysteresis parameter in the electrical characteristics tablesGo
  • Added the VCM test condition to the CMTI parameter in the electrical characteristics tables. Also updated the minimum value from 70 to 100 and deleted the maximum value of 100Go
  • Changed tfs To: tDO in Switching Characteristics—5-V SupplyGo
  • Changed tfs To: tDO in Switching Characteristics—3.3-V SupplyGo
  • Changed tfs To: tDO in Switching Characteristics—2.5-V SupplyGo
  • Added the lifetime projection graphs for DW and DWW packages to the Insulation Characteristics Curves section Go
  • Changed the thermal derating curves in the Safety Limiting Values sectionGo
  • Changed 2.7 V To: 1.7 V, fs high To: default high, and fs low To: default low in Figure 15 Go
  • Changed Figure 20 Go

Changes from * Revision (July 2015) to A Revision

  • Changed From: 1-page Product Preview To: Production datasheetGo

5 Pin Configuration and Functions

DW and DWW Packages
16-Pin SOIC
Top View
ISO7830 ISO7830F po_sllseo2.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
EN2 10 I Output enable 2. Output pins on side 2 are enabled when EN2 is high or open and in high-impedance state when EN2 is low.
GND1 2, 8 — Ground connection for VCC1
GND2 9, 15 — Ground connection for VCC2
INA 3 I Input, channel A
INB 4 I Input, channel B
INC 5 I Input, channel C
OUTA 14 O Output, channel A
OUTB 13 O Output, channel B
OUTC 12 O Output, channel C
NC 6, 7, 11 — Not connected
VCC1 1 — Power supply, side 1
VCC2 16 — Power supply, side 2

6 Specifications

6.1 Absolute Maximum Ratings

See (1)
MIN MAX UNIT
VCC1
VCC2 		Supply voltage(2) –0.5 6 V
V Voltage at INx, OUTx, or EN2x –0.5 VCCx + 0.5(3) V
IO Output current –15 15 mA
TJ Junction temperature –55 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak voltage values.
(3) Maximum voltage must not exceed 6 V

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±6000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC1, VCC2 Supply voltage 2.25 5.5 V
IOH High-level output current VCCO(1) = 5 V –4 mA
VCCO(1) = 3.3 V –2
VCCO(1) = 2.5 V –1
IOL Low-level output current VCCO(1) = 5 V 4 mA
VCCO(1) = 3.3 V 2
VCCO(1) = 2.5 V 1
VIH High-level input voltage 0.7 × VCCI(1) VCCI(1) V
VIL Low-level input voltage 0 0.3 × VCCI(1) V
DR Signaling rate 0 100 Mbps
TA Ambient temperature –55 25 125 °C
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

6.4 Thermal Information

THERMAL METRIC(1) ISO7830 UNIT
DW (SOIC) DWW (SOIC)
16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 81.1 83.4 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 43.8 45.2 °C/W
RθJB Junction-to-board thermal resistance 45.7 54.1 °C/W
ψJT Junction-to-top characterization parameter 17.0 17.6 °C/W
ψJB Junction-to-board characterization parameter 45.2 53.3 °C/W
RθJC(bottom) Junction-to-case(bottom) thermal resistance — — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Power Rating

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PD Maximum power dissipation VCC1 = VCC2 = 5.5 V, TJ = 150°C,
CL = 15 pF, input a 50 MHz 50% duty cycle square wave 		150 mW
PD1 Maximum power dissipation by side-1 25 mW
PD2 Maximum power dissipation by side-2 125 mW

6.6 Insulation Characteristics

PARAMETER TEST CONDITIONS SPECIFICATION UNIT
DW DWW
CLR External clearance(1) Shortest terminal-to-terminal distance through air >8 >14.5 mm
CPG External creepage(1) Shortest terminal-to-terminal distance across the package surface >8 >14.5 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) >21 >21 μm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A >600 >600 V
Material group I I
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 600 VRMS I–IV I–IV
Rated mains voltage ≤ 1000 VRMS I–III I–IV
DIN V VDE V 0884–10 (VDE V 0884–10):2006-12(2)
VIOWM Maximum isolation working voltage Time dependent dielectric breakdown (TDDB) Test; see Figure 1 and Figure 2 1500 2000 VRMS
2121 2828 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM
t = 60 s (qualification)
t= 1 s (100% production)		 8000 8000 VPK
VIOSM Maximum surge isolation voltage for reinforced insulation(3) Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)		 8000 8000 VPK
VIORM Maximum repetitive peak isolation voltage 2121 2828 VPK
VPR Input-to-output test voltage Method a, After Input/Output safety test subgroup 2/3,
VPR = VIORM × 1.2, t = 10 s,
Partial discharge < 5 pC		 2545 3394 VPK
Method a, After environmental tests subgroup 1,
VPR = VIORM × 1.6, t = 10 s,
Partial Discharge < 5 pC		 3394 4525
Method b1,
VPR = VIORM × 1.875, t = 1 s (100% Production test)
Partial discharge < 5 pC		 3977 5303
CIO Barrier capacitance, input to output(4) VIO = 0.4 × sin (2πft), f = 1 MHz ~1 ~1 pF
RIO Isolation resistance, input to output(4) VIO = 500 V, TA = 25°C >1012 >1012 Ω
VIO = 500 V, 100°C ≤ TA ≤ max >1011 >1011 Ω
RS Isolation resistance VIO = 500 V at TS >109 >109 Ω
Pollution degree 2 2
Climatic category 55/125/21 55/125/21
UL 1577
VISO Withstanding isolation voltage VTEST = VISO = 5700 VRMS, t = 60 s (qualification),
VTEST = 1.2 × VISO = 6840 VRMS, t = 1 s (100% production)		 5700 5700 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) All pins on each side of the barrier tied together creating a two-terminal device.

6.7 Regulatory Information

All DW package certifications are complete. DWW package certifications are complete for UL, VDE and TUV and planned for CSA and CQC.
VDE CSA UL CQC TUV
Certified according to DIN V VDE V 0884–10 (VDE V 0884–10):2006-12 and DIN EN 60950-1 (VDE 0805 Teil 1):2011-01 Approved under CSA Component Acceptance Notice 5A, IEC 60950-1 and IEC 60601-1 Certified according to UL 1577 Component Recognition Program Certified according to GB 4943.1-2011 Certified according to
EN 61010-1:2010 (3rd Ed) and
EN 60950-1:2006/A11:2009/A1:2010/
A12:2011/A2:2013
Reinforced insulation
Maximum transient isolation voltage, 8000 VPK;
Maximum repetitive peak isolation voltage, 2121 VPK (DW), 2828 VPK (DWW);
Maximum surge isolation voltage, 8000 VPK		 Reinforced insulation per CSA 60950-1-07+A1+A2 and IEC 60950-1 2nd Ed., 800 VRMS (DW) and 1450 VRMS (DWW) maximum working voltage (pollution degree 2, material group I); Single protection, 5700 VRMS Reinforced Insulation, Altitude ≤ 5000 m, Tropical Climate, 250 VRMS maximum working voltage 5700 VRMS Reinforced insulation per
EN 61010-1:2010 (3rd Ed) up to working voltage of 600 VRMS (DW package) and 1000 VRMS (DWW package)
2 MOPP (Means of Patient Protection) per CSA 60601-1:14 and IEC 60601-1 Ed. 3.1, 250 VRMS (354 VPK) maximum working voltage 5700 VRMS Reinforced insulation per
EN 60950-1:2006/A11:2009/A1:2010/
A12:2011/A2:2013 up to working voltage of 800 VRMS (DW package) and 1450 VRMS (DWW package)
Certificate number: 40040142 Master contract number: 220991 File number: E181974 Certificate number: CQC15001121716 Client ID number: 77311

6.8 Safety Limiting Values

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DW PACKAGE
IS Safety input, output, or supply current RθJA = 81.1°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 3 280 mA
RθJA = 81.1°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 3 428
RθJA = 81.1°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 3 560
PS Safety input, output, or total power RθJA = 81.1°C/W, TJ = 150°C, TA = 25°C, see Figure 5 1541 mW
TS Maximum safety temperature 150 °C
DWW PACKAGE
IS Safety input, output, or supply current RθJA = 83.4°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 4 273 mA
RθJA = 83.4°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 4 416
RθJA = 83.4°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 4 545
PS Safety input, output, or total power RθJA = 83.4°C/W, TJ = 150°C, TA = 25°C, see Figure 6 1499 mW
TS Maximum safety temperature 150 °C

The maximum safety temperature is the maximum junction temperature specified for the device. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information is that of a device installed on a high-K test board for leaded surface mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.

6.9 Electrical Characteristics—5-V Supply

VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –4 mA; see Figure 13 VCCO(1) – 0.4 VCCO – 0.2 V
VOL Low-level output voltage IOL = 4 mA; see Figure 13 0.2 0.4 V
VI(HYS) Input threshold voltage hysteresis 0.1 × VCCI(1) V
IIH High-level input current VIH = VCCI at INx or EN2 10 μA
IIL Low-level input current VIL = 0 V at INx or EN2 –10 μA
CMTI Common-mode transient immunity VI = VCCI or 0 V, VCM = 1500 V; see Figure 16 100 kV/μs
CI Input capacitance (2) VI = VCC / 2 + 0.4 × sin (2πft), f = 1 MHz, VCC = 5 V 2 pF
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.
(2) Measured from input pin to ground.

6.10 Supply Current Characteristics—5-V Supply

VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS SUPPLY CURRENT MIN TYP MAX UNIT
Supply current - disable EN2 = 0 V, VI = 0 V (Devices with suffix F),
VI = VCCI (Devices without suffix F) 		ICC1 1.1 1.8 mA
ICC2 0.4 0.6
EN2 = 0 V, VI = VCCI (Devices with suffix F),
VI = 0 V (Devices without suffix F) 		ICC1 4.6 6.6
ICC2 0.4 0.6
Supply current - DC signal VI = 0 V (Devices with suffix F),
VI = VCCI (Devices without suffix F) 		ICC1 1.1 2
ICC2 1.7 2.7
VI = VCCI (Devices with suffix F),
VI = 0 V (Devices without suffix F) 		ICC1 4.6 6.8
ICC2 1.9 2.8
Supply current - AC signal All channels switching with square wave clock input;
CL = 15 pF		 1 Mbps ICC1 2.8 4.4
ICC2 1.9 3
10 Mbps ICC1 2.9 4.4
ICC2 3.3 4.6
100 Mbps ICC1 3.9 4.9
ICC2 17.5 20.8

6.11 Electrical Characteristics—3.3-V Supply

VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –2 mA; see Figure 13 VCCO(1) – 0.4 VCCO – 0.2 V
VOL Low-level output voltage IOL = 2 mA; see Figure 13 0.2 0.4 V
VI(HYS) Input threshold voltage hysteresis 0.1 × VCCI(1) V
IIH High-level input current VIH = VCCI at INx or EN2 10 μA
IIL Low-level input current VIL = 0 V at INx or EN2 –10 μA
CMTI Common-mode transient immunity VI = VCCI or 0 V, VCM = 1500 V; see Figure 16 100 kV/μs
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

6.12 Supply Current Characteristics—3.3-V Supply

VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS SUPPLY CURRENT MIN TYP MAX UNIT
Supply current - disable EN2 = 0 V, VI = 0 V (Devices with suffix F),
VI = VCCI (Devices without suffix F) 		ICC1 1.1 1.8 mA
ICC2 0.3 0.6
EN2 = 0 V, VI = VCCI (Devices with suffix F),
VI = 0 V (Devices without suffix F) 		ICC1 4.6 6.6
ICC2 0.3 0.6
Supply current - DC signal VI = 0 V (Devices with suffix F),
VI = VCCI (Devices without suffix F) 		ICC1 1.1 2
ICC2 1.7 2.6
VI = VCCI (Devices with suffix F),
VI = 0 V (Devices without suffix F) 		ICC1 4.6 6.8
ICC2 1.9 2.8
Supply current - AC signal All channels switching with square wave clock input;
CL = 15 pF		 1 Mbps ICC1 2.8 4.4
ICC2 1.9 2.9
10 Mbps ICC1 2.9 4.4
ICC2 2.9 4.1
100 Mbps ICC1 3.5 4.8
ICC2 13.2 16

6.13 Electrical Characteristics—2.5-V Supply

VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –1 mA; see Figure 13 VCCO(1) – 0.4 VCCO – 0.2 V
VOL Low-level output voltage IOL = 1 mA; see Figure 13 0.2 0.4 V
VI(HYS) Input threshold voltage hysteresis 0.1 × VCCI(1) V
IIH High-level input current VIH = VCCI at INx or EN2 10 μA
IIL Low-level input current VIL = 0 V at INx or EN2 –10 μA
CMTI Common-mode transient immunity VI = VCCI or 0 V, VCM = 1500 V; see Figure 16 100 kV/μs
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

6.14 Supply Current Characteristics—2.5-V Supply

VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS SUPPLY CURRENT MIN TYP MAX UNIT
Supply current - disable EN2 = 0 V, VI = 0 V (Devices with suffix F),
VI = VCCI (Devices without suffix F) 		ICC1 1.1 1.8 mA
ICC2 0.3 0.6
EN2 = 0 V, VI = VCCI (Devices with suffix F),
VI = 0 V (Devices without suffix F) 		ICC1 4.6 6.6
ICC2 0.3 0.6
Supply current - DC signal VI = 0 V (Devices with suffix F),
VI = VCCI (Devices without suffix F) 		ICC1 1.1 2
ICC2 1.7 2.6
VI = VCCI (Devices with suffix F),
VI = 0 V (Devices without suffix F) 		ICC1 4.6 6.8
ICC2 1.8 2.8
Supply current - AC signal All channels switching with square wave clock input;
CL = 15 pF		 1 Mbps ICC1 2.8 4.4
ICC2 1.8 2.9
10 Mbps ICC1 2.9 4.4
ICC2 2.6 3.7
100 Mbps ICC1 3.4 4.7
ICC2 10.3 12.7

6.15 Switching Characteristics—5-V Supply

VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 13 6 11 16 ns
PWD Pulse width distortion(1) |tPHL – tPLH| 0.55 4.1 ns
tsk(o) Channel-to-channel output skew time(2) Same-direction channels 2.5 ns
tsk(pp) Part-to-part skew time(3) 4.5 ns
tr Output signal rise time See Figure 13 1.7 3.9 ns
tf Output signal fall time 1.9 3.9 ns
tPHZ Disable propagation delay, high-to-high impedance output See Figure 14 12 20 ns
tPLZ Disable propagation delay, low-to-high impedance output 12 20 ns
tPZH Enable propagation delay, high impedance-to-high output for ISO7830 10 20 ns
Enable propagation delay, high impedance-to-high output for ISO7830F 2 2.5 μs
tPZL Enable propagation delay, high impedance-to-low output for ISO7830 2 2.5 μs
Enable propagation delay, high impedance-to-low output for ISO7830F 10 20 ns
tDO Default output delay time from input power loss Measured from the time VCC goes below 1.7 V. See Figure 15 0.2 9 μs
tie Time interval error 216 – 1 PRBS data at 100 Mbps 0.90 ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

6.16 Switching Characteristics—3.3-V Supply

VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 13 6 10.8 16 ns
PWD Pulse width distortion(1) |tPHL – tPLH| 0.7 4.2 ns
tsk(o) Channel-to-channel output skew time(2) Same-direction channels 2.2 ns
tsk(pp) Part-to-part skew time(3) 4.5 ns
tr Output signal rise time See Figure 13 0.8 3 ns
tf Output signal fall time 0.8 3 ns
tPHZ Disable propagation delay, high-to-high impedance output See Figure 14 17 32 ns
tPLZ Disable propagation delay, low-to-high impedance output 17 32 ns
tPZH Enable propagation delay, high impedance-to-high output for ISO7830 17 32 ns
Enable propagation delay, high impedance-to-high output for ISO7830F 2 2.5 μs
tPZL Enable propagation delay, high impedance-to-low output for ISO7830 2 2.5 μs
Enable propagation delay, high impedance-to-low output for ISO7830F 17 32 ns
tDO Default output delay time from input power loss Measured from the time VCC goes below 1.7 V. See Figure 15 0.2 9 μs
tie Time interval error 216 – 1 PRBS data at 100 Mbps 0.91 ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

6.17 Switching Characteristics—2.5-V Supply

VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 13 7.5 11.7 17.5 ns
PWD Pulse width distortion(1) |tPHL – tPLH| 0.66 4.2 ns
tsk(o) Channel-to-channel output skew time(2) Same-direction Channels 2.2 ns
tsk(pp) Part-to-part skew time(3) 4.5 ns
tr Output signal rise time See Figure 13 1 3.5 ns
tf Output signal fall time 1.2 3.5 ns
tPHZ Disable propagation delay, high-to-high impedance output See Figure 14 22 45 ns
tPLZ Disable propagation delay, low-to-high impedance output 22 45 ns
tPZH Enable propagation delay, high impedance-to-high output for ISO7830 18 45 ns
Enable propagation delay, high impedance-to-high output for ISO7830F 2 2.5 μs
tPZL Enable propagation delay, high impedance-to-low output for ISO7830 2 2.5 μs
Enable propagation delay, high impedance-to-low output for ISO7830F 18 45 ns
tDO Default output delay time from input power loss Measured from the time VCC goes below 1.7 V. See Figure 15 0.2 9 μs
tie Time interval error 216 – 1 PRBS data at 100 Mbps 0.91 ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

6.18 Insulation Characteristics Curves

ISO7830 ISO7830F tddb_curve_reinforced_dw.gif
TA upto 150°C Operating lifetime = 135 years
Stress-voltage frequency = 60 Hz
Isolation working voltage = 1500 VRMS
Figure 1. Reinforced Isolation Capacitor Lifetime Projection for Devices in DW Package
ISO7830 ISO7830F D014_sllseo2.gif Figure 3. Thermal Derating Curve for Safety Limiting Current for DW Package
ISO7830 ISO7830F D016_sllseo2.gif Figure 5. Thermal Derating Curve for Safety Limiting Power for DW Package
ISO7830 ISO7830F tddb_curve_reinforced_dww.gif
TA upto 150°C Operating lifetime = 34 years
Stress-voltage frequency = 60 Hz
Isolation working voltage = 2000 VRMS
Figure 2. Reinforced Isolation Capacitor Lifetime Projection for Devices in DWW Package
ISO7830 ISO7830F D015_sllseo2.gif Figure 4. Thermal Derating Curve for Safety Limiting Current for DWW Package
ISO7830 ISO7830F D017_sllseo2.gif Figure 6. Thermal Derating Curve for Safety Limiting Power for DWW Package

6.19 Typical Characteristics

ISO7830 ISO7830F D001_SLLSEO2.gif
TA = 25°C CL = 15 pF
Figure 7. Supply Current vs Data Rate (With 15-pF Load)
ISO7830 ISO7830F D003_SLLSEJ0.gif
TA = 25°C
Figure 9. High-Level Output Voltage vs High-level Output Current
ISO7830 ISO7830F D005_SLLSEJ0.gif
Figure 11. Power Supply Undervoltage Threshold vs Free-Air Temperature
ISO7830 ISO7830F D002_SLLSEO2.gif
TA = 25°C CL = No Load
Figure 8. Supply Current vs Data Rate (With No Load)
ISO7830 ISO7830F D004_SLLSEJ0.gif
TA = 25°C
Figure 10. Low-Level Output Voltage vs Low-Level Output Current
ISO7830 ISO7830F D006_SLLSEJ0.gif
Figure 12. Propagation Delay Time vs Free-Air Temperature

7 Parameter Measurement Information

ISO7830 ISO7830F switch_test_circuit_sllsek9.gif
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in actual application.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 13. Switching Characteristics Test Circuit and Voltage Waveforms
ISO7830 ISO7830F delay_tim_llsek9.gif
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 10 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 14. Enable/Disable Propagation Delay Time Test Circuit and Waveform
ISO7830 ISO7830F failsafe_sllsep1.gif
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 15. Default Output Delay Time Test Circuit and Voltage Waveforms
ISO7830 ISO7830F com_tran_imm_test_circ_sllsek9.gif
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 16. Common-Mode Transient Immunity Test Circuit

8 Detailed Description

8.1 Overview

The ISO7830x device has an ON-OFF keying (OOK) modulation scheme to transmit the digital data across a silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier to represent one digital state and sends no signal to represent the other digital state. The receiver demodulates the signal after advanced signal conditioning and produces the output through a buffer stage. If the EN pin is low then the output goes to high impedance. The ISO7830x device also incorporates advanced circuit techniques to maximize the CMTI performance and minimize the radiated emissions because of the high frequency carrier and IO buffer switching. The conceptual block diagram of a digital capacitive isolator, Figure 17, shows a functional block diagram of a typical channel.

8.2 Functional Block Diagram

ISO7830 ISO7830F fbd_sllsej0.gif Figure 17. Conceptual Block Diagram of a Digital Capacitive Isolator

Figure 18 shows a conceptual detail of how the ON-OFF keying scheme works.

ISO7830 ISO7830F on_off_keying_sllsej0.gif Figure 18. On-Off Keying (OOK) Based Modulation Scheme

8.3 Feature Description

Table 1 provides an overview of the device features.

Table 1. Device Features

PART NUMBER CHANNEL DIRECTION RATED ISOLATION MAXIMUM DATA RATE DEFAULT OUTPUT
ISO7830 3 Forward, 0 Reverse
5700 VRMS / 8000 VPK(1) 100 Mbps High
ISO7830F 3 Forward, 0 Reverse
5700 VRMS / 8000 VPK(1) 100 Mbps Low
(1) See the Regulatory Information section for detailed isolation ratings.

8.3.1 Electromagnetic Compatibility (EMC) Considerations

Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge (ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level performance and reliability depends, to a large extent, on the application board design and layout, the ISO7830x device incorporates many chip-level design improvements for overall system robustness. Some of these improvements include:

  • Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
  • Low-resistance connectivity of ESD cells to supply and ground pins.
  • Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
  • Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance path.
  • PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic SCRs.
  • Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.

8.4 Device Functional Modes

Table 2 lists the ISO7830x functional modes.

Table 2. Function Table(1)

VCCI VCCO INPUT
(INx)(3)		 OUTPUT ENABLE
(EN2)		 OUTPUT
(OUTx)		 COMMENTS
PU PU H H or open H Normal Operation:
A channel output assumes the logic state of the input.
L H or open L
Open H or open Default Default mode: When INx is open, the corresponding channel output goes to its default logic state. Default is High for ISO7830 and Low for ISO7830F
X PU X L Z A low value of output enable causes the outputs to be high-impedance
PD PU X H or open Default Default mode: When VCCI is unpowered, a channel output assumes the logic state based on the selected default option. Default is High for ISO7830 and Low for ISO7830F
When VCCI transitions from unpowered to powered-up, a channel output assumes the logic state of the input.
When VCCI transitions from powered-up to unpowered, channel output assumes the selected default state.
X PD X X Undetermined When VCCO is unpowered, a channel output state is undetermined (2).
When VCCO transitions from unpowered to powered-up, a channel output assumes the logic state of the input
(1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 2.25 V); PD = Powered down (VCC ≤ 1.7 V); X = Irrelevant; H = High level; L = Low level ; Z = High Impedance
(2) The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V.
(3) A strongly driven input signal can weakly power the floating VCC via an internal protection diode and cause undetermined output.

8.4.1 Device I/O Schematics

ISO7830 ISO7830F device_IO_schematic_sllseo2.gif Figure 19. Device I/O Schematics

 
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