SLLSEN2 Data sheet

SLLSEN2B July 2015 – April 2016 ISO7840

PRODUCTION DATA.

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

DWW|16
DW|16

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

See ⁽¹⁾

			MIN	MAX	UNIT
V_CC1, V_CC2	Supply voltage⁽²⁾		–0.5	6	V
	Voltage	INx	–0.5	V_CCX + 0.5⁽³⁾	V
		OUTx	–0.5	V_CCX + 0.5⁽³⁾
		EN2	–0.5	V_CCX + 0.5⁽³⁾
I_O	Output current		–15	15	mA
	Surge immunity			12.8	kV
T_stg	Storage temperature		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak voltage values.

(3) Maximum voltage must not exceed 6 V

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±6000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

			MIN	NOM	MAX	UNIT
V_CC1, V_CC2	Supply voltage		2.25		5.5	V
I_OH	High-level output current	V_CCO⁽²⁾ = 5 V	–4			mA
		V_CCO⁽²⁾ = 3.3 V	–2
		V_CCO⁽²⁾ = 2.5 V	–1
I_OL	Low-level output current	V_CCO⁽²⁾ = 5 V			4	mA
		V_CCO⁽²⁾ = 3.3 V			2
		V_CCO⁽²⁾ = 2.5 V			1
V_IH	High-level input voltage		0.7 × V_CCI ⁽²⁾		V_CCI ⁽²⁾	V
V_IL	Low-level input voltage		0		0.3 × V_CCI⁽²⁾	V
DR	Signaling rate		0		100	Mbps
T_J	Junction temperature⁽¹⁾		–55		150	°C
T_A	Ambient temperature		–55	25	125	°C

(1) To maintain the recommended operating conditions for T_J, see Thermal Information.

(2) V_CCI = Input-side V_CC; V_CCO = Output-side V_CC.

6.4 Thermal Information

		ISO7840		UNIT
THERMAL METRIC⁽¹⁾		DW (SOIC)	DWW (SOIC)
THERMAL METRIC⁽¹⁾		16 Pins	16 Pins
R_θJA	Junction-to-ambient thermal resistance	78.9	78.9	°C/W
R_θJC(top)	Junction-to-case(top) thermal resistance	41.6	41.1	°C/W
R_θJB	Junction-to-board thermal resistance	43.6	49.5	°C/W
ψ_JT	Junction-to-top characterization parameter	15.5	15.2	°C/W
ψ_JB	Junction-to-board characterization parameter	43.1	48.8	°C/W
R_θJC(bottom)	Junction-to-case(bottom) thermal resistance	N/A	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Power Ratings

V_CC1 = V_CC2 = 5.5 V, T_J = 150°C, C_L = 15 pF, input a 50 MHz 50% duty cycle square wave

PARAMETER		MAX	UNIT
P_D	Maximum power dissipation by ISO7840x	200	mW
P_D1	Maximum power dissipation by side-1 of ISO7840x	40	mW
P_D2	Maximum power dissipation by side-2 of ISO7840x	160	mW

6.6 Insulation Specifications

PARAMETER		TEST CONDITIONS	SPECIFICATION		UNIT
PARAMETER		TEST CONDITIONS	DW	DWW	UNIT
GENERAL
CLR	External clearance⁽¹⁾	Shortest pin-to-pin distance through air	>8	>14.5	mm
CPG	External creepage⁽¹⁾	Shortest pin-to-pin distance across the package surfaceHigh Voltage Feature Description	>8	>14.5	mm
DTI	Distance through the insulation	Minimum internal gap (internal clearance)	>21	>21	μm
CTI	Comparative tracking index	DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A	>600	>600	V
	Material group		I	I
	Overvoltage category per IEC 60664-1	Rated mains voltage ≤ 600 V_RMS	I–IV	I–IV
	Overvoltage category per IEC 60664-1	Rated mains voltage ≤ 1000 V_RMS	I–III	I–IV
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12⁽²⁾
V_IORM	Maximum repetitive peak isolation voltage		2121	2828	V_PK
V_IOWM	Maximum isolation working voltage	AC voltage (sine wave); Time dependent dielectric breakdown (TDDB) Test, see Figure 1 and Figure 2	1500	2000	V_RMS
V_IOWM	Maximum isolation working voltage	DC voltage	2121	2828	V_DC
V_IOTM	Maximum transient isolation voltage	V_TEST = V_IOTM t = 60 s (qualification) t= 1 s (100% production)	8000	8000	V_PK
V_IOSM	Maximum surge isolation voltage⁽³⁾	Test method per IEC 60065, 1.2/50 µs waveform, V_TEST = 1.6 × V_IOSM = 12800 V_PK (qualification)	8000	8000	V_PK
q_pd	Apparent charge⁽⁴⁾	Method a: After I/O safety test subgroup 2/3, V_ini = V_IOTM, t_ini = 60 s; V_pd(m) = 1.2 × V_IORM = 2545 V_PK (DW) and 3394 V_PK (DWW), t_m = 10 s	≤5	≤5	pC
		Method a: After environmental tests subgroup 1, V_ini = V_IOTM, t_ini = 60 s; V_pd(m) = 1.6 × V_IORM = 3394 V_PK (DW) and 4525 V_PK (DWW), t_m = 10 s	≤5	≤5
		Method b1: At routine test (100% production) and preconditioning (type test) V_ini = V_IOTM, t_ini = 1 s; V_pd(m) = 1.875 × V_IORM = 3977 V_PK (DW) and 5303 V_PK (DWW), t_m = 1 s	≤5	≤5
C_IO	Barrier capacitance, input to output⁽⁵⁾	V_IO = 0.4 × sin (2πft), f = 1 MHz	2	2	pF
R_IO	Isolation resistance, input to output⁽⁵⁾	V_IO = 500 V, T_A = 25°C	>10¹²	>10¹²	Ω
		V_IO = 500 V, 100°C ≤ T_A ≤ 125°C	>10¹¹	>10¹¹
		V_IO = 500 V at T_S = 150°C	>10⁹	>10⁹
	Pollution degree		2	2
	Climatic category		55/125/21	55/125/21
UL 1577
V_ISO	Withstand isolation voltage	V_TEST = V_ISO = 5700 V_RMS, t = 60 s (qualification), V_TEST = 1.2 × V_ISO = 6840 V_RMS, t = 1 s (100% production)	5700	5700	V_RMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-pin device.

6.7 Safety-Related Certifications

Certifications for the DW package are complete. DWW package certifications are complete for UL, VDE and TUV and planned for CSA and CQC.

VDE	CSA	UL	CQC	TUV
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN 60950-1 (VDE 0805 Teil 1):2011-01	Approved under CSA Component Acceptance Notice 5A, IEC 60950-1 and IEC 60601-1	Certified according to UL 1577 Component Recognition Program	Certified according to GB 4943.1-2011	Certified according to EN 61010-1:2010 (3rd Ed) and EN 60950-1:2006/A11:2009/A1:2010/ A12:2011/A2:2013
Reinforced insulation Maximum transient isolation voltage, 8000 V_PK; Maximum repetitive peak isolation voltage, 2121 V_PK (DW), 2828 V_PK (DWW); Maximum surge isolation voltage, 8000 V_PK	Reinforced insulation per CSA 60950-1-07+A1+A2 and IEC 60950-1 2nd Ed., 800 V_RMS (DW package) and 1450 V_RMS (DWW package) max working voltage (pollution degree 2, material group I); 2 MOPP (Means of Patient Protection) per CSA 60601-1:14 and IEC 60601-1 Ed. 3.1, 250 V_RMS (354 V_PK) max working voltage (DW package)	Single protection, 5700 V_RMS	Reinforced Insulation, Altitude ≤ 5000 m, Tropical Climate, 250 V_RMS maximum working voltage	5700 V_RMS Reinforced insulation per EN 61010-1:2010 (3rd Ed) up to working voltage of 600 V_RMS (DW package) and 1000 V_RMS (DWW package) 5700 V_RMS Reinforced insulation per EN 60950-1:2006/A11:2009/A1:2010/ A12:2011/A2:2013 up to working voltage of 800 V_RMS (DW package) and 1450 V_RMS (DWW package)
Certificate number: 40040142	Master contract number: 220991	File number: E181974	Certificate number: CQC15001121716	Client ID number: 77311

6.8 Safety Limiting Values

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures.

PARAMETER		TEST CONDITIONS	MAX	UNIT
I_S	Safety input, output, or supply current	R_θJA = 78.9°C/W, V_I = 5.5 V, T_J = 150°C, T_A = 25°C	288	mA
		R_θJA = 78.9°C/W, V_I = 3.6 V, T_J = 150°C, T_A = 25°C	440
		R_θJA = 78.9°C/W, V_I = 2.75 V, T_J = 150°C, T_A = 25°C	576
P_S	Safety input, output, or total power	R_θJA = 78.9°C/W, T_J = 150°C, T_A = 25°C	1584	mW
T_S	Maximum safety temperature		150	°C

The maximum safety temperature is the maximum junction temperature specified for the device. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.

6.9 Electrical Characteristics—5-V Supply

V_CC1 = V_CC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	I_OH = –4 mA; see Figure 11	V_CCO – 0.4	V_CCO – 0.2		V
V_OL	Low-level output voltage	I_OL = 4 mA; see Figure 11		0.2	0.4	V
V_I(HYS)	Input threshold voltage hysteresis		0.1 × V_CCI			V
I_IH	High-level input current	V_IH = V_CCI at INx or EN2			10	μA
I_IL	Low-level input current	V_IL = 0 V at INx or EN2	–10			μA
CMTI	Common-mode transient immunity	V_I = V_CCI or 0 V, V_CM = 1500 V; see Figure 14	100			kV/μs
C_I	Input capacitance	V_I = V_CC/2 + 0.4 × sin (2πft), f = 1 MHz, V_CC = 5 V		2		pF

6.10 Supply Characteristics—5-V Supply

V_CC1 = V_CC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)

PARAMETER	TEST CONDITIONS			SUPPLY CURRENT	TYP	MAX	UNIT
Supply current	Disable	EN2 = 0 V, V_I = 0 V (ISO7840F), V_I = V_CCI⁽¹⁾ (ISO7840)		I_CC1	1.3	2	mA
		EN2 = 0 V, V_I = 0 V (ISO7840F), V_I = V_CCI⁽¹⁾ (ISO7840)		I_CC2	0.4	0.6	mA
		EN2 = 0 V, V_I = V_CCI (ISO7840F), V_I = 0 V (ISO7840) EN2 = 0 V		I_CC1	6	8.5	mA
				I_CC2	0.4	0.6	mA
	DC signal	V_I = 0 V (ISO7840F), V_I = V_CCI (ISO7840)		I_CC1	1.3	2	mA
		V_I = 0 V (ISO7840F), V_I = V_CCI (ISO7840)		I_CC2	2.2	3.1	mA
		V_I = V_CCI (ISO7840F), V_I = 0 V (ISO7840)		I_CC1	5.9	8.6	mA
		V_I = V_CCI (ISO7840F), V_I = 0 V (ISO7840)		I_CC2	2.5	3.3	mA
	All channels switching with square wave clock input; C_L = 15 pF	1 Mbps		I_CC1	3.6	5.3	mA
		1 Mbps		I_CC2	2.6	3.7	mA
		10 Mbps		I_CC1	3.8	5.4	mA
		10 Mbps		I_CC2	4.5	5.9	mA
		100 Mbps	DW package	I_CC1	5.1	5.9	mA
			DW package	I_CC2	23.8	27.4	mA
			DWW package	I_CC1	5.1	5.9	mA
			DWW package	I_CC2	23.8	28.5	mA

(1) V_CCI = Input-side V_CC; V_CCO = Output-side V_CC.

6.11 Electrical Characteristics—3.3-V Supply

V_CC1 = V_CC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	I_OH = –2 mA; see Figure 11	V_CCO – 0.4	V_CCO – 0.2		V
V_OL	Low-level output voltage	I_OL = 2 mA; see Figure 11		0.2	0.4	V
V_I(HYS)	Input threshold voltage hysteresis		0.1 × V_CCI			V
I_IH	High-level input current	V_IH = V_CCI at INx or EN2			10	μA
I_IL	Low-level input current	V_IL = 0 V at INx or EN2	–10			μA
CMTI	Common-mode transient immunity	V_I = V_CCI or 0 V, V_CM = 1500 V; see Figure 14	100			kV/μs

6.12 Supply Current Characteristics—3.3-V Supply

V_CC1 = V_CC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)

PARAMETER	TEST CONDITIONS		SUPPLY CURRENT	TYP	MAX	UNIT
Supply current	Disable	EN2 = 0 V, V_I = 0 V (ISO7840F), V_I = V_CCI⁽¹⁾ (ISO7840)	I_CC1	1.3	2	mA
		EN2 = 0 V, V_I = 0 V (ISO7840F), V_I = V_CCI⁽¹⁾ (ISO7840)	I_CC2	0.4	0.6	mA
		EN2 = 0 V, V_I = V_CCI⁽¹⁾ (ISO7840F), V_I = 0 V (ISO7840)	I_CC1	6	8.5	mA
		EN2 = 0 V, V_I = V_CCI⁽¹⁾ (ISO7840F), V_I = 0 V (ISO7840)	I_CC2	0.4	0.6	mA
	DC signal	V_I = 0 V (ISO7840F), V_I = V_CCI⁽¹⁾ (ISO7840)	I_CC1	1.3	2	mA
		V_I = 0 V (ISO7840F), V_I = V_CCI⁽¹⁾ (ISO7840)	I_CC2	2.2	3	mA
		V_I = V_CCI⁽¹⁾ (ISO7840F), V_I = 0 V (ISO7840)	I_CC1	5.9	8.6	mA
		V_I = V_CCI⁽¹⁾ (ISO7840F), V_I = 0 V (ISO7840)	I_CC2	2.4	3.3	mA
	All channels switching with square wave clock input; C_L = 15 pF	1 Mbps	I_CC1	3.6	5.3	mA
		1 Mbps	I_CC2	2.5	3.6	mA
		10 Mbps	I_CC1	3.7	5.3	mA
		10 Mbps	I_CC2	3.9	5.1	mA
		100 Mbps	I_CC1	4.5	5.8	mA
		100 Mbps	I_CC2	17.7	20.6	mA

(1) V_CCI = Input-side V_CC; V_CCO = Output-side V_CC.

6.13 Electrical Characteristics—2.5-V Supply

V_CC1 = V_CC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	I_OH = –1 mA; see Figure 11	V_CCO – 0.4	V_CCO – 0.2		V
V_OL	Low-level output voltage	I_OL = 1 mA; see Figure 11		0.2	0.4	V
V_I(HYS)	Input threshold voltage hysteresis		0.1 × V_CCI			V
I_IH	High-level input current	V_IH = V_CCI at INx or EN2			10	μA
I_IL	Low-level input current	V_IL = 0 V at INx or EN2	–10			μA
CMTI	Common-mode transient immunity	V_I = V_CCI or 0 V, V_CM = 1500 V; see Figure 14	100			kV/μs

6.14 Supply Current Characteristics—2.5-V Supply

V_CC1 = V_CC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)

PARAMETER	TEST CONDITIONS		SUPPLY CURRENT	TYP	MAX	UNIT
Supply current	Disable	EN2 = 0 V, V_I = 0 V (Devices with suffix F), V_I = V_CCI⁽¹⁾ (Devices without suffix F)	I_CC1	1.3	2	mA
			I_CC2	0.4	0.6	mA
		EN2 = 0 V, V_I = V_CCI⁽¹⁾ (Devices with suffix F), V_I = 0 V (Devices without suffix F)	I_CC1	6	8.5	mA
			I_CC2	0.4	0.6	mA
	DC signal	V_I = 0 V (Devices with suffix F), V_I = V_CCI⁽¹⁾ (Devices without suffix F)	I_CC1	1.3	2	mA
			I_CC2	2.2	3	mA
		V_I = V_CCI⁽¹⁾ (Devices with suffix F), V_I = 0 V (Devices without suffix F)	I_CC1	5.9	8.6	mA
			I_CC2	2.4	3.3	mA
	All channels switching with square wave clock input; C_L = 15 pF	1 Mbps	I_CC1	3.6	5.3	mA
		1 Mbps	I_CC2	2.5	3.5	mA
		10 Mbps	I_CC1	3.7	5.3	mA
		10 Mbps	I_CC2	3.5	4.7	mA
		100 Mbps	I_CC1	4.4	5.7	mA
		100 Mbps	I_CC2	13.9	16.4	mA

(1) V_CCI = Input-side V_CC; V_CCO = Output-side V_CC.

6.15 Switching Characteristics—5-V Supply

V_CC1 = V_CC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_PLH, t_PHL	Propagation delay time	See Figure 11	6	11	16	ns
PWD	Pulse width distortion⁽¹⁾ \|t_PHL – t_PLH\|	See Figure 11		0.55	4.1	ns
t_sk(o)	Channel-to-channel output skew time⁽²⁾	Same-direction channels			2.5	ns
t_sk(pp)	Part-to-part skew time⁽³⁾				4.5	ns
t_r	Output signal rise time	See Figure 11		1.7	3.9	ns
t_f	Output signal fall time	See Figure 11		1.9	3.9	ns
t_PHZ	Disable propagation delay, high-to-high impedance output	See Figure 12		12	20	ns
t_PLZ	Disable propagation delay, low-to-high impedance output			12	20	ns
t_PZH	Enable propagation delay, high impedance-to-high output for ISO7840			10	20	ns
t_PZH	Enable propagation delay, high impedance-to-high output for ISO7840F			2	2.5	μs
t_PZL	Enable propagation delay, high impedance-to-low output for ISO7840			2	2.5	μs
t_PZL	Enable propagation delay, high impedance-to-low output for ISO7840F			10	20	ns
t_fs	Default output delay time from input power loss	Measured from the time V_CC goes below 1.7 V. See Figure 13		0.2	9	μs
t_ie	Time interval error	2¹⁶ – 1 PRBS data at 100 Mbps		0.90		ns

(1) Also known as pulse skew.

(2) t_sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.

(3) t_sk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

6.16 Switching Characteristics—3.3-V Supply

V_CC1 = V_CC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_PLH, t_PHL	Propagation delay time	See Figure 11	6	10.8	16	ns
PWD	Pulse width distortion⁽¹⁾ \|t_PHL – t_PLH\|	See Figure 11		0.7	4.2	ns
t_sk(o)	Channel-to-channel output skew time⁽²⁾	Same-direction channels			2.2	ns
t_sk(pp)	Part-to-part skew time⁽³⁾				4.5	ns
t_r	Output signal rise time	See Figure 11		0.8	3	ns
t_f	Output signal fall time	See Figure 11		0.8	3	ns
t_PHZ	Disable propagation delay, high-to-high impedance output	See Figure 12		17	32	ns
t_PLZ	Disable propagation delay, low-to-high impedance output			17	32	ns
t_PZH	Enable propagation delay, high impedance-to-high output for ISO7840			17	32	ns
t_PZH	Enable propagation delay, high impedance-to-high output for ISO7840F			2	2.5	μs
t_PZL	Enable propagation delay, high impedance-to-low output for ISO7840			2	2.5	μs
t_PZL	Enable propagation delay, high impedance-to-low output for ISO7840F			17	32	ns
t_fs	Default output delay time from input power loss	Measured from the time V_CC goes below 1.7 V. See Figure 13		0.2	9	μs
t_ie	Time interval error	2¹⁶ – 1 PRBS data at 100 Mbps		0.91		ns

(1) Also known as Pulse Skew.

(2) t_sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.

6.17 Switching Characteristics—2.5-V Supply

V_CC1 = V_CC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_PLH, t_PHL	Propagation delay time	See Figure 11	7.5	11.7	17.5	ns
PWD	Pulse width distortion⁽¹⁾ \|t_PHL – t_PLH\|	See Figure 11		0.66	4.2	ns
t_sk(o)	Channel-to-channel output skew time⁽²⁾	Same-direction Channels			2.2	ns
t_sk(pp)	Part-to-part skew time⁽³⁾				4.5	ns
t_r	Output signal rise time	See Figure 11		1	3.5	ns
t_f	Output signal fall time	See Figure 11		1.2	3.5	ns
t_PHZ	Disable propagation delay, high-to-high impedance output	See Figure 12		22	45	ns
t_PLZ	Disable propagation delay, low-to-high impedance output			22	45	ns
t_PZH	Enable propagation delay, high impedance-to-high output for ISO7840			18	45	ns
t_PZH	Enable propagation delay, high impedance-to-high output for ISO7840F			2	2.5	μs
t_PZL	Enable propagation delay, high impedance-to-low output for ISO7840			2	2.5	μs
t_PZL	Enable propagation delay, high impedance-to-low output for ISO7840F			18	45	ns
t_fs	Default output delay time from input power loss	Measured from the time V_CC goes below 1.7 V. See Figure 13		0.2	9	μs
t_ie	Time interval error	2¹⁶ – 1 PRBS data at 100 Mbps		0.91		ns

(1) Also known as pulse skew.

(2) t_sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.