SLLSEJ0H October 2014 – March 2024 ISO7842
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
tPLH, tPHL | Propagation delay time | See Figure 6-1 | 6 | 11 | 16 | ns | |
PWD | Pulse width distortion(1) |tPHL – tPLH| | 0.55 | 4.1 | ns | |||
tsk(o) | Channel-to-channel output skew time(2) | Same-direction channels | 2.5 | ns | |||
tsk(pp) | Part-to-part skew time(3) | 4.5 | ns | ||||
tr | Output signal rise time | See Figure 6-1 | 1.7 | 3.9 | ns | ||
tf | Output signal fall time | 1.9 | 3.9 | ns | |||
tPHZ | Disable propagation delay, high-to-high impedance output | See Figure 6-2 | 12 | 20 | ns | ||
tPLZ | Disable propagation delay, low-to-high impedance output | 12 | 20 | ns | |||
tPZH | Enable propagation delay, high impedance-to-high output for ISO7842 | 10 | 20 | ns | |||
Enable propagation delay, high impedance-to-high output for ISO7842F | 2 | 2.5 | μs | ||||
tPZL | Enable propagation delay, high impedance-to-low output for ISO7842 | 2 | 2.5 | μs | |||
Enable propagation delay, high impedance-to-low output for ISO7842F | 10 | 20 | ns | ||||
tfs | Default output delay time from input power loss | Measured from the time VCC goes below 1.7 V. See Figure 6-3 | 0.2 | 9 | μs | ||
tie | Time interval error | 216 – 1 PRBS data at 100 Mbps | 0.90 | ns |