SLLSFW0A April   2024  – May 2024 ISOM8610

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
  7. 6 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Sizing RIN
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DFG|4
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Insulation Specifications

PARAMETERTEST CONDITIONSVALUEUNIT
4-DFG
IEC 60664-1
CLRExternal clearance(1)Side 1 to side 2 distance through air> 5mm
CPGExternal creepage(1)Side 1 to side 2 distance across package surface> 5mm
DTIDistance through the insulationMinimum internal gap (internal clearance)>17µm
CTIComparative tracking indexIEC 60112; UL 746A>400V
Material GroupAccording to IEC 60664-1II
Overvoltage category per IEC 60664-1Rated mains voltage ≤ 150VRMSI-IV
Rated mains voltage ≤ 300VRMSI-IV
Rated mains voltage ≤ 600VRMSI-III
DIN EN IEC 60747-17 (VDE 0884-17) (2)
VIORMMaximum repetitive peak isolation voltageAC voltage (bipolar)707VPK
VIOWMMaximum isolation working voltageAC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test500VRMS
DC voltage707VDC
VIOTMMaximum transient isolation voltageVTEST = VIOTM, t = 60s (qualification); VTEST = 1.2 × VIOTM, t = 1s (100% production)5303VPK
VIMPMaximum impulse voltage(3)Tested in air, 1.2/50µs waveform per IEC 62368-17200VPK
VIOSMMaximum surge isolation voltage(3)Test method per IEC 62368-1, 1.2/50µs waveform,
VTEST = 1.6 × VIMP  or min 10 kVPK (qualification)		6250VPK
qpdApparent charge(4)Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60s; Vpd(m) = 1.2 × VIORM, tm = 10s≤ 5pC
Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60s;
Vpd(m) = 1.6 × VIORM, tm = 10s		≤ 5
Method b: At routine test (100% production), Vini = 1.2 × VIOTM, tini = 1s;
Vpd(m) = 1.875 × VIORM, tm = 1s (method b1) or
Vpd(m) = Vini, tm = tini (method b3)		≤ 5
CIOBarrier capacitance, input to output(5)VIO = 0.4 × sin (2 πft), f = 1MHz1pF
RIOInsulation resistance, input to output(5)VIO = 500V,  TA = 25°C> 1012Ω
VIO = 500V,  100°C ≤ TA ≤ 125°C> 1011
VIO = 500V at  TS = 150°C> 109
Pollution degree2
Climatic category55/125/21
UL 1577
VISOWithstand isolation voltageVTEST = VISO, t = 60s (qualification); VTEST = 1.2 × VISO , t = 1s (100% production)3750VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) Testing is carried out in air to determine the surge immunity of the package.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.