SNIS232A October   2023  – June 2024 ISOTMP35

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Insulation Specification
    6. 5.6  Power Ratings
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Features Description
      1. 6.3.1 Integrated Isolation Barrier and Thermal Response
      2. 6.3.2 Analog Output
        1. 6.3.2.1 Output Accuracy
        2. 6.3.2.2 Output Voltage Linearity
        3. 6.3.2.3 Drive Capability
        4. 6.3.2.4 Common Mode Transient Immunity (CMTI)
      3. 6.3.3 Thermal Response
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Output Voltage Linearity
      2. 7.1.2 Load Regulation
      3. 7.1.3 Start-Up Settling Time
      4. 7.1.4 Thermal Response
      5. 7.1.5 External Buffer
      6. 7.1.6 ADC Selection and Impact on Accuracy
      7. 7.1.7 Implementation Guidelines
      8. 7.1.8 PSRR
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Insulation Lifetime
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DFQ|7
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Insulation Specification

Over free-air temperature range and VDD = 2.3V to 5.5V (unless otherwise noted); Typical specifications are at TA = 25°C and VDD = 3.3V (unless otherwise noted)
PARAMETER TEST CONDITIONS VALUE UNIT
GENERAL
CLR External Clearance(1) Shortest terminal-to-terminal distance through air >4 mm
CPG External Creepage(1) Shortest terminal-to-terminal distance across the package surface >4 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) >17 µm
CTI Comparative tracking index DIN EN 60112; IEC 60112 >400 V
Material Group II
Overvoltage category Rated mains voltage ≤ 150VRMS I-IV
Rated mains voltage ≤ 300VRMS I-III
DIN EN IEC 60747-17 (VDE 0884-17)
VIORM Maximum repetitive peak isolation voltage At AC voltage 707 VPK
VIOWM Maximum-rated isolation working voltage At AC voltage (sine wave) 500 VRMS
At DC voltage 707 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60s (qualification test),
VTEST = 1.2 × VIOTM, t = 1s (100% production test)		 4250 VPK
VIMP Maximum impulse voltage(2) Tested in air, 1.2/50-μs waveform per IEC 62368-1 5000  VPK
VIOSM Maximum surge isolation voltage(3) Tested in oil (qualification test),
1.2/50-μs waveform per IEC 62368-1		 6500  VPK
qpd Apparent charge(4) Method a, after input/output safety test subgroups 2 and 3,
Vpd(ini) = VIOTM, tini = 60s, Vpd(m) = 1.2 × VIORM, tm = 10s		 ≤ 5 pC
Method a, after environmental tests subgroup 1,
Vpd(ini) = VIOTM, tini = 60s, Vpd(m) = 1.3 × VIORM, tm = 10s		 ≤ 5
Method b1, at preconditioning (type test) and routine test,
Vpd(ini) = VIOTM, tini = 1s, Vpd(m) = 1.5 × VIORM, tm = 1s		 ≤ 5
Method b2, at routine test (100% production)(6),
Vpd(ini) = VIOTM = Vpd(m); tini = tm = 1s		 ≤ 5
CIO Barrier capacitance,
input to output(5)		 VIO = 0.1VPP at 100kHz 1.4  pF
RIO Insulation resistance,
input to output(5)		 VIO = 500V at TA = 25°C >1012  Ω
VIO = 500V at 100°C ≤ TA ≤ 125°C >1011 
VIO = 500V at TA = 150°C >109 
Pollution degree 2
Climatic category 55/125/21
UL1577
VISO Withstand isolation voltage VTEST = VISO, t = 60s (qualification);
VTEST = 1.2 × VISO, t = 1s (100% production)		 3000 VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Take care to maintain the creepage and clearance distance of the board design to make sure that the mounting pads of the isolator on the printed circuit board do not reduce this distance. Creepage and clearance on a printed circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) Testing is carried out in air to determine the surge immunity of the isolation barrier.
(3) Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device.
(6) Either method b1 or b2 is used in production.