SLLSFW6 March   2024 ISOUSB211-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Insulation Characteristics Curves
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Test Circuits
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power Supply Options
      2. 7.3.2  Power Up
      3. 7.3.3  Symmetric Operation, Dual-Role Port and Role-Reversal
      4. 7.3.4  Connect and Speed Detection
      5. 7.3.5  Disconnect Detection
      6. 7.3.6  Reset
      7. 7.3.7  LS/FS Message Traffic
      8. 7.3.8  HS Message Traffic
      9. 7.3.9  Equalization and Pre-emphasis
      10. 7.3.10 L2 Power Management State (Suspend) and Resume
      11. 7.3.11 L1 Power Management State (Sleep) and Resume
      12. 7.3.12 HS Test Mode Support
      13. 7.3.13 CDP Advertising
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Typical Application
      1. 8.1.1 Isolated Host or Hub
      2. 8.1.2 Isolated Peripheral - Self-Powered
      3. 8.1.3 Isolated Peripheral - Bus-Powered
      4. 8.1.4 Application Curve
        1. 8.1.4.1 Insulation Lifetime
    2. 8.2 Meeting USB2.0 HS Eye-Diagram Specifications
    3. 8.3 Thermal Considerations
      1. 8.3.1 VBUS / V3P3V Power
      2. 8.3.2 VCCx / V1P8Vx Power
      3. 8.3.3 Example Configuration 1
      4. 8.3.4 Example Configuration 2
      5. 8.3.5 Example Configuration 3
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Layout Example
        2. 8.5.1.2 PCB Material
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
  • DP|28
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

GUID-20200818-CA0I-SDPH-FR7W-Z6MTWNZQ27QN-low.svgFigure 4-1 DP Package 28-Pin SSOP Top View
Table 4-1 Pin Functions—28 Pins
PINI/ODESCRIPTION
NO.NAME
1VBUS1—Input Power Supply for Side 1. If a 4.25 V to 5.5 V (example USB power bus) supply is available connect it to VBUS1. In this case an internal LDO generates V3P3V1. Else, connect VBUS1 and V3P3V1 to an external 3.3 V power supply.
2V3P3V1—Power Supply for Side 1. If a 4.25 V to 5.5 V supply is connected to VBUS1 connect a bypass capacitor between V3P3V1 and GND1. In this case an internal LDO generates V3P3V1. Else, connect VBUS1 and V3P3V1 to an external 3.3 V power supply.
3GND1—Ground 1. Ground reference for Isolator Side 1.
4V1P8V1—Power Supply for Side 1. If a 2.4 V to 5.5 V supply is connected to VCC1 connect a bypass capacitor between V1P8V1 and GND1. In this case an internal LDO generates V1P8V1. Else, connect VCC1 and V1P8V1 to an external 1.8 V power supply.
5VCC1—Input Power Supply for Side 1. If a 2.4 V to 5.5 V (example USB power bus, or a DC-DC supply derived from USB power bus) supply is available connect it to VCC1. In this case an internal LDO generates V1P8V1. Else, connect VCC1 and V1P8V1 to an external 1.8 V power supply.
6V2OKOHigh level on this pin indicates that side 2 is powered up.
7UD-I/OUpstream facing port D-.
8UD+I/OUpstream facing port D+.
9EQ10IEqualization setting for Side 1, LSB. Logic Input.
10EQ11IEqualization setting for Side 1, MSB. Logic Input.
11V1P8V1—Connect pin 11 to pin 4, with local bypass capacitors near pin 11.
12GND1—Ground 1. Ground reference for Isolator Side 1.
13CDPENZ1IActive low singal. Enables CDP advertising on UD+/UD- pins.
14NC—Leave floating or connect to V3P3V1.
15NC—Leave floating or connect to V3P3V2.
16CDPENZ2IActive low singal. Enables CDP advertising on DD+/DD- pins.
17GND2—Ground 2. Ground reference for Isolator Side 2.
18V1P8V2—Connect pin 18 to pin 25, with local bypass capacitors near pin 18.
19EQ21IEqualization setting for Side 2, MSB. Logic Input.
20EQ20IEqualization setting for Side 2, LSB. Logic Input.
21DD+I/ODownstream facing port D+.
22DD-I/ODownstream facing port D-.
23V1OKOHigh level on this pin indicates that side 1 is powered up.
24VCC2—Input Power Supply for Side 2. If a 2.4 V to 5.5 V (example USB power bus, or a DC-DC supply derived from USB power bus) supply is available connect it to VCC2. In this case an internal LDO generates V1P8V2. Else, connect VCC2 and V1P8V2 to an external 1.8 V power supply.
25V1P8V2—Power Supply for Side 1. If a 2.4 V to 5.5 V supply is connected to VCC2 connect a bypass capacitor between V1P8V2 and GND2. In this case an internal LDO generates V1P8V2. Else, connect VCC2 and V1P8V2 to an external 1.8 V power supply.
26GND2—Ground 2. Ground reference for Isolator Side 2.
27V3P3V2—Power Supply for Side 2. If a 4.25 V to 5.5 V supply is connected to VBUS2 connect a bypass capacitor between V3P3V2 and GND1. In this case an internal LDO generates V3P3V2. Else, connect VBUS2 and V3P3V2 to an external 3.3 V power supply.
28VBUS2—Input Power Supply for Side 2. If a 4.25 V to 5.5 V (example USB power bus) supply is available connect it to VBUS2. In this case an internal LDO generates V3P3V2. Else, connect VBUS2 and V3P3V2 to an external 3.3 V power supply.