SWRS289 october   2021 IWR2243

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Revision History
  7. 6 Device Comparison
    1. 6.1 Related Products
  8. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Power-On Hours (POH)
    4. 8.4 Recommended Operating Conditions
    5. 8.5 Power Supply Specifications
    6. 8.6 Power Consumption Summary
    7. 8.7 RF Specification
    8. 8.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 8.9 Timing and Switching Characteristics
      1. 8.9.1 Power Supply Sequencing and Reset Timing
      2. 8.9.2 Synchronized Frame Triggering
      3. 8.9.3 Input Clocks and Oscillators
        1. 8.9.3.1 Clock Specifications
      4. 8.9.4 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 8.9.4.1 Peripheral Description
          1. 8.9.4.1.1 SPI Timing Conditions
          2. 8.9.4.1.2 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
          3. 8.9.4.1.3 SPI Peripheral Mode Timing Requirements (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        2. 8.9.4.2 Typical Interface Protocol Diagram (Peripheral Mode)
      5. 8.9.5 Inter-Integrated Circuit Interface (I2C)
        1. 8.9.5.1 I2C Timing Requirements
      6. 8.9.6 Quad Serial Peripheral Interface (QSPI)
        1. 8.9.6.1 QSPI Timing Conditions
        2. 8.9.6.2 Timing Requirements for QSPI Input (Read) Timings
        3. 8.9.6.3 QSPI Switching Characteristics
      7. 8.9.7 LVDS Interface Configuration
        1. 8.9.7.1 LVDS Interface Timings
      8. 8.9.8 General-Purpose Input/Output
        1. 8.9.8.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      9. 8.9.9 Camera Serial Interface (CSI)
        1. 8.9.9.1 CSI Switching Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Subsystems
      1. 9.3.1 RF and Analog Subsystem
        1. 9.3.1.1 Clock Subsystem
        2. 9.3.1.2 Transmit Subsystem
        3. 9.3.1.3 Receive Subsystem
      2. 9.3.2 Host Interface
    4. 9.4 Other Subsystems
      1. 9.4.1 ADC Data Format Over CSI2 Interface
      2. 9.4.2 ADC Channels (Service) for User Application
        1. 9.4.2.1 GPADC Parameters
  11. 10Monitoring and Diagnostic Mechanisms
  12. 11Applications, Implementation, and Layout
    1. 11.1 Application Information
    2. 11.2 Imaging Radar using Cascade Configuration
    3. 11.3 Reference Schematic
    4. 11.4 Layout
      1. 11.4.1 Layout Guidelines
      2. 11.4.2 Stackup Details
  13. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Export Control Notice
    8. 12.8 Glossary
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.7 RF Specification

over recommended operating conditions and with run time calibrations enabled (unless otherwise noted)
PARAMETERMINTYPMAXUNIT
ReceiverNoise figure13dB
1-dB compression point (Out Of Band)(1)–9dBm
Maximum gain52dB
Gain range20dB
Gain step size2dB
Image Rejection Ratio (IMRR)30dB
IF bandwidth(2)20MHz
ADC sampling rate
(Real/ Complex 2x)		 45Msps
ADC sampling rate
(Complex 1x)		22.5Msps
ADC resolution12Bits
Return loss (S11)<–10dB
Gain mismatch variation (over temperature)±0.5dB
Phase mismatch variation (over temperature)±3°
In-band IIP2

RX gain = 30dB
IF = 1.5, 2 MHz at -12 dBFS

16dBm
Out-of-band IIP2

RX gain = 24dB
IF = 10 KHz at -10 dBm,
1.9 MHz at -30 dBm

24dBm
Idle Channel Spurs–90dBFS
TransmitterOutput power13dBm
Phase shifter accuracy±5°
Amplitude noise–145dBc/Hz
Clock subsystemFrequency range7681GHz
Ramp rate266(3)MHz/µs
Phase noise at 1-MHz offset76 to 78 GHz (VCO1)(4)–96dBc/Hz
76 to 81 GHz (VCO2)–94
20 GHz SYNC OUT signal (FM_CW_CLKOUT and FM_CW_SYNCOUT)Frequency range1920.25GHz
Output power at the pin3710dBm
Return loss–9dB

Impedance

50

Ω
20 GHz SYNC IN signal (FM_CW_SYNCIN)Frequency range1920.25GHz
Input power at the pin-67(5)dBm
Return loss–10dB
Impedance50Ω
(1) 1-dB Compression Point (Out Of Band) is measured by feeding a continuous wave tone below the lowest HPF cut-off frequency (10 kHz).
(2) The analog IF stages include high-pass filtering, with two independently configurable first-order high-pass corner frequencies. The set of available HPF corners is summarized as follows:
Available HPF Corner Frequencies (kHz)
HPF1 HPF2
175,235,350,700 350, 700, 1400, 2800
The filtering performed by the digital baseband chain is targeted to provide:
  • Less than ±0.5 dB pass-band ripple/droop, and
  • Better than 60 dB anti-aliasing attenuation for any frequency that can alias back into the pass-band.
(3) The max ramp rate depends on the PLL bandwidth configuration set using the"AWR_APLL_SYNTH_BW_CONTROL_SB" API. For more details, see the mmWave Interface Control Document.
(4) The phase noise numbers use the following configuration: SYNTH ICP TRIM = 3 , SYNTH RZ TRIM = 8 , and APLL ICP TRIM = 0x26.
(5) At 105°C TJ, the max input level recommended is 3 dBm

Figure 8-1 shows variations of noise figure and in-band P1dB parameters with respect to receiver gain programmed.

GUID-63849C3C-4306-4BC6-9C5D-51991E8F7277-low.gifFigure 8-1 Noise Figure, In-band P1dB vs Receiver Gain