SWRS289 october   2021 IWR2243

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Revision History
  7. 6 Device Comparison
    1. 6.1 Related Products
  8. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Power-On Hours (POH)
    4. 8.4 Recommended Operating Conditions
    5. 8.5 Power Supply Specifications
    6. 8.6 Power Consumption Summary
    7. 8.7 RF Specification
    8. 8.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 8.9 Timing and Switching Characteristics
      1. 8.9.1 Power Supply Sequencing and Reset Timing
      2. 8.9.2 Synchronized Frame Triggering
      3. 8.9.3 Input Clocks and Oscillators
        1. 8.9.3.1 Clock Specifications
      4. 8.9.4 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 8.9.4.1 Peripheral Description
          1. 8.9.4.1.1 SPI Timing Conditions
          2. 8.9.4.1.2 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
          3. 8.9.4.1.3 SPI Peripheral Mode Timing Requirements (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        2. 8.9.4.2 Typical Interface Protocol Diagram (Peripheral Mode)
      5. 8.9.5 Inter-Integrated Circuit Interface (I2C)
        1. 8.9.5.1 I2C Timing Requirements
      6. 8.9.6 Quad Serial Peripheral Interface (QSPI)
        1. 8.9.6.1 QSPI Timing Conditions
        2. 8.9.6.2 Timing Requirements for QSPI Input (Read) Timings
        3. 8.9.6.3 QSPI Switching Characteristics
      7. 8.9.7 LVDS Interface Configuration
        1. 8.9.7.1 LVDS Interface Timings
      8. 8.9.8 General-Purpose Input/Output
        1. 8.9.8.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      9. 8.9.9 Camera Serial Interface (CSI)
        1. 8.9.9.1 CSI Switching Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Subsystems
      1. 9.3.1 RF and Analog Subsystem
        1. 9.3.1.1 Clock Subsystem
        2. 9.3.1.2 Transmit Subsystem
        3. 9.3.1.3 Receive Subsystem
      2. 9.3.2 Host Interface
    4. 9.4 Other Subsystems
      1. 9.4.1 ADC Data Format Over CSI2 Interface
      2. 9.4.2 ADC Channels (Service) for User Application
        1. 9.4.2.1 GPADC Parameters
  11. 10Monitoring and Diagnostic Mechanisms
  12. 11Applications, Implementation, and Layout
    1. 11.1 Application Information
    2. 11.2 Imaging Radar using Cascade Configuration
    3. 11.3 Reference Schematic
    4. 11.4 Layout
      1. 11.4.1 Layout Guidelines
      2. 11.4.2 Stackup Details
  13. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Export Control Notice
    8. 12.8 Glossary
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.9.9.1 CSI Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETERMINTYPMAXUNIT
HPTX
HSTXDBRData bit rate(1/2/4 data lane PHY)150600Mbps
fCLKDDR clock frequency(1/2/4 data lane PHY)75300MHz
ΔVCMTX(LF)Common-level variation–5050mV
tR and tF20% to 80% rise time and fall time0.3UI
LPTX DRIVER
tEOTTime from start of THS-TRAIL period to start of LP-11 state105 + 12*UIns
DATA-CLOCK Timing Specification
UINOMNominal Unit Interval1.6713.33ns
UIINST,MINMinimum instantaneous Unit Interval1.131ns
TSKEW[TX]Data to clock skew measured at transmitter–0.150.15UIINST,MIN
CSI2 TIMING SPECIFICATION
TCLK-PRETime that the HS clock shall be driven by the transmitter before any associated data lane beginning the transition from LP to HS mode.8ns
TCLK-PREPARETime that the transmitter drives the clock lane LP-00 line state immediately before the HS-0 line state starting the HS transmission.3895ns
TCLK-PREPARE + TCLK-ZEROTCLK-PREPARE + time that the transmitter drives the HS-0 state before starting the clock.300ns
TEOTTransmitted time interval from the start of THS-TRAIL or TCLKTRAIL, to the start of the LP-11 state following a HS burst.105 ns + 12*UIns
THS-PREPARETime that the transmitter drives the data lane LP-00 line state immediately before the HS-0 line state starting the HS transmission40 + 4*UI85 + 6*UIns
THS-PREPARE + THS-ZEROTHS-PREPARE + time that the transmitter drives the HS-0 state prior to transmitting the Sync sequence.145 ns + 10*UIns
THS-EXITTime that the transmitter drives LP-11 following a HS burst.100ns
THS-TRAILTime that the transmitter drives the flipped differential state after last payload data bit of a HS transmission burstmax(8*UI, 60 ns + 4*UI)ns
TLPXTXXXransmitted length of any low-power state period50ns
GUID-ACBA4F70-195A-4E2E-B208-A179855673EE-low.gifFigure 8-12 Clock and Data Timing in HS Transmission
GUID-A11035FE-6965-443E-A80C-1E88CE0B21A6-low.gifFigure 8-13 High-Speed Data Transmission Burst
GUID-C6385BA1-7B1E-480E-A6AF-4EE394799342-low.gif
A. The HS to LP transition of the CLK does not actually take place since the CLK is always ON in HS mode.
Figure 8-14 Switching the Clock Lane Between Clock Transmission and Low-Power Mode