SWRS330 May   2024 IWR2944

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configurations and Functions
    1. 5.1 Pin Diagram
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions - Digital
    4. 5.4 Signal Descriptions - Analog
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Power-On Hours (POH)
    4. 6.4  Recommended Operating Conditions
    5. 6.5  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.5.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.5.2 Hardware Requirements
      3. 6.5.3 Impact to Your Hardware Warranty
    6. 6.6  Power Supply Specifications
    7. 6.7  Power Consumption Summary
    8. 6.8  RF Specifications
    9. 6.9  Thermal Resistance Characteristics
    10. 6.10 Power Supply Sequencing and Reset Timing
    11. 6.11 Input Clocks and Oscillators
      1. 6.11.1 Clock Specifications
    12. 6.12 Peripheral Information
      1. 6.12.1  QSPI Flash Memory Peripheral
        1. 6.12.1.1 QSPI Timing Conditions
        2. 6.12.1.2 QSPI Timing Requirements #GUID-CD30070D-F132-4A2C-92CD-5AA96AE70B94/GUID-97D19708-D87E-443B-9ADF-1760CFEF6F4C #GUID-CD30070D-F132-4A2C-92CD-5AA96AE70B94/GUID-0A61EEC9-2B95-4C27-B219-18D27C8F9430
        3. 6.12.1.3 QSPI Switching Characteristics #GUID-20B35D26-AFE6-451C-B9E9-B3F2FA08097C/T4362547-64 #GUID-20B35D26-AFE6-451C-B9E9-B3F2FA08097C/T4362547-65
      2. 6.12.2  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 6.12.2.1 MibSPI Peripheral Description
        2. 6.12.2.2 MibSPI Transmit and Receive RAM Organization
          1. 6.12.2.2.1 SPI Timing Conditions
          2. 6.12.2.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-20BA2ACF-4FC2-43F6-960F-1A4CA56E65A6/T4362547-236 #GUID-20BA2ACF-4FC2-43F6-960F-1A4CA56E65A6/T4362547-237 #GUID-20BA2ACF-4FC2-43F6-960F-1A4CA56E65A6/T4362547-238
          3. 6.12.2.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-517E5284-3345-461F-B07F-EB95741B1272/T4362547-244 #GUID-517E5284-3345-461F-B07F-EB95741B1272/T4362547-245 #GUID-517E5284-3345-461F-B07F-EB95741B1272/T4362547-246
        3. 6.12.2.3 SPI Peripheral Mode I/O Timings
          1. 6.12.2.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) #GUID-5C88F9F6-787B-49E2-984F-02158AB0C326/T4362547-70 #GUID-5C88F9F6-787B-49E2-984F-02158AB0C326/T4362547-71 #GUID-5C88F9F6-787B-49E2-984F-02158AB0C326/T4362547-73
      3. 6.12.3  Ethernet Switch (RGMII/RMII/MII) Peripheral
        1. 6.12.3.1  RGMII/MII Timing Conditions
        2. 6.12.3.2  RGMII Transmit Clock Switching Characteristics
        3. 6.12.3.3  RGMII Transmit Data and Control Switching Characteristics
        4. 6.12.3.4  RGMII Receive Clock Timing Requirements
        5. 6.12.3.5  RGMII Receive Data and Control Timing Requirements
        6. 6.12.3.6  RMII Transmit Clock Switching Characteristics
        7. 6.12.3.7  RMII Transmit Data and Control Switching Characteristics
        8. 6.12.3.8  RMII Receive Clock Timing Requirements
        9. 6.12.3.9  RMII Receive Data and Control Timing Requirements
        10. 6.12.3.10 MII Transmit Switching Characteristics
        11. 6.12.3.11 MII Receive Clock Timing Requirements
        12. 6.12.3.12 MII Receive Timing Requirements
        13. 6.12.3.13 MII Transmit Clock Timing Requirements
        14. 6.12.3.14 MDIO Interface Timings
      4. 6.12.4  LVDS/Aurora Instrumentation and Measurement Peripheral
        1. 6.12.4.1 LVDS Interface Configuration
        2. 6.12.4.2 LVDS Interface Timings
      5. 6.12.5  UART Peripheral
        1. 6.12.5.1 SCI Timing Requirements
      6. 6.12.6  Inter-Integrated Circuit Interface (I2C)
        1. 6.12.6.1 I2C Timing Requirements #GUID-437677C7-D935-4733-A64D-553EFECA73F7/T4362547-185
      7. 6.12.7  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 6.12.7.1 Dynamic Characteristics for the CAN-FD TX and RX Pins
      8. 6.12.8  CSI2 Receiver Peripheral
        1. 6.12.8.1 CSI2 Switching Characteristics
      9. 6.12.9  Enhanced Pulse-Width Modulator (ePWM)
      10. 6.12.10 General-Purpose Input/Output
        1. 6.12.10.1 Switching Characteristics for Output Timing versus Load Capacitance (CL) #GUID-46919170-3C9C-440C-879B-A7700B77517D/T4362547-45 #GUID-46919170-3C9C-440C-879B-A7700B77517D/T4362547-50
    13. 6.13 Emulation and Debug
      1. 6.13.1 Emulation and Debug Description
      2. 6.13.2 JTAG Interface
        1. 6.13.2.1 Timing Requirements for IEEE 1149.1 JTAG
        2. 6.13.2.2 Switching Characteristics for IEEE 1149.1 JTAG
      3. 6.13.3 ETM Trace Interface
        1. 6.13.3.1 ETM TRACE Timing Requirements
        2. 6.13.3.2 ETM TRACE Switching Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Subsystems
      1. 7.3.1 RF and Analog Subsystem
        1. 7.3.1.1 RF Clock Subsystem
        2. 7.3.1.2 Transmit Subsystem
        3. 7.3.1.3 Receive Subsystem
      2. 7.3.2 Processor Subsystem
    4. 7.4 Other Subsystems
      1. 7.4.1 Hardware Accelerator Subsystem
      2. 7.4.2 Security – Hardware Security Module
      3. 7.4.3 ADC Channels (Service) for User Application
  9. 8 Monitoring and Diagnostics
    1. 8.1 Monitoring and Diagnostic Mechanisms
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Application Information
    2. 9.2 Short and Medium Range Radar
    3. 9.3 Reference Schematic
  11. 10Device and Documentation Support
    1. 10.1 Device Support
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.3 Signal Descriptions - Digital

Note: All digital IO pins of the device (except NERROR_OUT and WARM_RESET) are non-failsafe; hence, care needs to be taken that they are not driven externally without the VIO supply being present to the device.
Note: The GPIO state during the power supply ramp is not ensured. In case the GPIO is used in the application where the state of the GPIO is critical, even when NRESET is low , a tri-state buffer should be used to isolate the GPIO output from the radar device and a pull resister used to define the required state in the application. The NRESET signal to the radar device could be used to control the output enable (OE) of the tri-state buffer.
Note: ROM bootloader uses only B16 (MSS_UARTA_RX) and C16 (MSS_UARTA_TX) pins for flash programming. It is recommended to use these pins while building the module.
Table 5-1 Signal Descriptions - Digital
FUNCTIONSIGNAL NAMEPIN TYPEDESCRIPTIONPIN NUMBER
SPI InterfaceMSS_MIBSPIA_CLKIOSPI Channel A - ClockT16
MSS_MIBSPIA_MOSIIOSPI Channel A - Controller Out Peripheral InU15
MSS_MIBSPIA_MISOIOSPI Channel A - Controller In Peripheral OutU16
MSS_MIBSPIA_CS0IOSPI Channel A Chip Select T15
MSS_MIBSPIA_HOSTIRQOOut of Band Interrupt to an external host communicating over SPIV16,V17
MSS_MIBSPIB_CLK(1)IOSPI Channel B - ClockT13,R10
MSS_MIBSPIB_MOSI(1)IOSPI Channel B - Controller Out Peripheral InV12,V11
MSS_MIBSPIB_MISO(1)IOSPI Channel B - Controller In Peripheral OutU13,U11
MSS_MIBSPIB_CS0IOSPI Channel B Chip Select (Instance ID 0)U14,U12
MSS_MIBSPIB_CS1IOSPI Channel B Chip Select (Instance ID 1)V16,A16,R14
MSS_MIBSPIB_CS2IOSPI Channel B Chip Select (Instance ID 2)A16,V11,R14,V17
CAN-FDMSS_MCANA_RXICAN-FD A (MCAN) Receive SignalT13,R12,C14,F16,D16
MSS_MCANA_TXOCAN-FD A (MCAN) Transmit SignalU14,T11,C12,E17,D17
MSS_MCANB_RXICAN-FD B (MCAN) Receive SignalV12,A17
MSS_MCANB_TXOCAN-FD B (MCAN) Transmit SignalU13,B17
UART (MSS) MSS_UARTA_RXIOMain Subsystem - UART A Receive

(For Flash programming)

T13,D13,F16,P17,B16,A15
MSS_UARTA_TXIOMain Subsystem - UART A Transmit (For Flash programming)U14,D15,E17,U17,C16,B14,A14
MSS_UARTB_TXIOMain Subsystem - UART B ReceiveT13,U14,C12,D15,G15,E17,L15,U4,B16,A14
MSS_UARTB_RXIOMain Subsystem - UART B TransmitR17,F16,T7,C16
QSPI for Serial FlashMSS_QSPI_0IOQSPI Data Line #0 (Used with Serial Data Flash)U11
MSS_QSPI_1IQSPI Data Line #1 (Used with Serial Data Flash)V11
MSS_QSPI_2IQSPI Data Line #2 (Used with Serial Data Flash)T11
MSS_QSPI_3IQSPI Data Line #3 (Used with Serial Data Flash)R12
MSS_QSPI_CLKIOQSPI clock (Used with Serial Data Flash)R10
MSS_QSPI_CSOQSPI chip select (Used with Serial Data Flash)U12
I2C interface MSS_I2CA_SDAIOI2C ClockV12,E17,U17,R8
MSS_I2CA_SCLIOI2C DataU13,F16,P17,U9
RS232 UARTMSS_RS232_RXIODebug UART (Operates as Bus controller) - Receive SignalF16
MSS_RS232_TXIODebug UART (Operates as Bus controller) - Transmit SignalE17
PWM ModuleMSS_EPWMA0OPWM Module 1 - Output A0V12,R15,E17,E15,B17,R6
MSS_EPWMA1OPWM Module 1 - Output A1B15,T17,E17,C18,A17,U8
MSS_EPWMA_SYNCIIPWM Module 1 - Sync InputA16,D17
MSS_EPWMA_SYNCOOPWM Module 1 - Sync OutputD16
MSS_EPWMB0OPWM Module 2 - Output B0B15,U13,T17,R14,F16,E17,B17,C17,T7
MSS_EPWMB1OPWM Module 2 - Output B1R14,F16,A17,R8
MSS_EPWMB_SYNCIIPWM Module 2 - Sync InputT18,A14
MSS_EPWMB_SYNCOOPWM Module 2 - Sync OutputP16
MSS_EPWMC0OPWM Module 3 - Output C0T13,F16,E15,C17,U4
MSS_EPWMC1OPWM Module 3 - Output C1C18,U9
MSS_EPWMC_SYNCIIPWM Module 3 - Sync InputP17
MSS_EPWMC_SYNCOOPWM Module 3 - Sync OutputN15
MSS_EPWM_TZ0IPWM module Trip Signal 0G15,J15
MSS_EPWM_TZ1IPWM module Trip Signal 1A16,M16
MSS_EPWM_TZ2IPWM module Trip Signal 2B15,L15
RGMII/RMII/MII EthernetMSS_MII_COLI

MSS Ethernet MII Collision Detect

U8
MSS_MII_CRSI

MSS Ethernet MII Carrier Sense

R8
MSS_MII_RXERIMSS Ethernet MII Receive ErrorU9
MSS_MII_TXENOMSS Ethernet MII Transmit EnableR6
MSS_MII_RXDVI

MSS Ethernet MII Receive Data Valid

T7
MSS_MII_TXD3OMSS Ethernet MII Transmit Data 3U4
MSS_MII_TXD2OMSS Ethernet MII Transmit Data 2U6
MSS_MII_TXD1OMSS Ethernet MII Transmit Data 1U5
MSS_MII_TXD0OMSS Ethernet MII Transmit Data 0U7
MSS_MII_TXCLKIMSS Ethernet MII Transmit ClockV3
MSS_MII_RXCLKIMSS Ethernet MII Receive ClockT9
MSS_MII_RXD3IMSS Ethernet MII Receive Data 3U10
MSS_MII_RXD2IMSS Ethernet MII Receive Data 2V5
MSS_MII_RXD1IMSS Ethernet MII Receive Data 1V4
MSS_MII_RXD0IMSS Ethernet MII Receive Data 0V6
MSS_RMII_REFCLKIOMSS Ethernet RMII Clock InputU8,T9
MSS_RMII_CRS_DVI

MSS Ethernet RMII Carrier Sense/Receive

Data Valid

R8,T7
MSS_RMII_RXERIMSS Ethernet RMII Receive ErrorU9
MSS_RMII_TXENOMSS Ethernet RMII Transmit EnableR6
MSS_RMII_TXD1OMSS Ethernet RMII Transmit Data 1U5
MSS_RMII_TXD0OMSS Ethernet RMII Transmit Data 0U7
MSS_RMII_RXD1IMSS Ethernet MII Receive Data 1V4
MSS_RMII_RXD0IMSS Ethernet MII Receive Data 0V6
MSS_RGMII_TCTLOMSS Ethernet RGMII Transmit ControlR6
MSS_RGMII_RCTLIMSS Ethernet RGMII Receive ControlT7
MSS_RGMII_TD3OMSS Ethernet RGMII Transmit Data 3U4
MSS_RGMII_TD2OMSS Ethernet RGMII Transmit Data 2U6
MSS_RGMII_TD1OMSS Ethernet RGMII Transmit Data 1U5
MSS_RGMII_TD0OMSS Ethernet RGMII Transmit Data 0U7
MSS_RGMII_TCLKOMSS Ethernet RGMII Transmit ClockV3
MSS_RGMII_RCLKIMSS Ethernet RGMII Receive ClockT9
MSS_RGMII_RD3IMSS Ethernet RGMII Receive Data 3U10
MSS_RGMII_RD2IMSS Ethernet RGMII Receive Data 2V5
MSS_RGMII_RD1IMSS Ethernet RGMII Receive Data 1V4
MSS_RGMII_RD0IMSS Ethernet RGMII Receive Data 0V6
MSS_MDIO_DATAIOMSS Ethernet Manage Data Input/Output dataT5
MSS_MDIO_CLKOMSS Ethernet Manage Data Input/Output ClockR4
MSS_CPTS0_TS_SYNCOEthernet Timestamp SYNC outputB16
MSS_CPTS0_HW2TSPUSHIEthernet hardware Timestamp Inputs PinsC16
MSS_CPTS0_HW1TSPUSHIA15
Trace SignalTRACE_DATA_0ODebug Trace Output - Data LineU17
TRACE_DATA_1ODebug Trace Output - Data LineP17
TRACE_DATA_2ODebug Trace Output - Data LineT18
TRACE_DATA_3ODebug Trace Output - Data LineN15
TRACE_DATA_4ODebug Trace Output - Data LineP16
TRACE_DATA_5ODebug Trace Output - Data LineL15
TRACE_DATA_6ODebug Trace Output - Data LineM16
TRACE_DATA_7ODebug Trace Output - Data LineJ15
TRACE_DATA_8ODebug Trace Output - Data LineD17
TRACE_DATA_9ODebug Trace Output - Data LineD16
TRACE_DATA_10ODebug Trace Output - Data LineE15
TRACE_DATA_11ODebug Trace Output - Data LineC18
TRACE_DATA_12ODebug Trace Output - Data LineB17
TRACE_DATA_13ODebug Trace Output - Data LineA17
TRACE_DATA_14ODebug Trace Output - Data LineC17
TRACE_CLKODebug Trace Output - ClockR15
TRACE_CTLODebug Trace Output - ControlT17
DMM InterfaceDMM0IDebug Interface (Hardware In Loop) - Data LineU17
DMM1IDebug Interface (Hardware In Loop) - Data LineP17
DMM2IDebug Interface (Hardware In Loop) - Data LineT18
DMM3IDebug Interface (Hardware In Loop) - Data LineN15
DMM4IDebug Interface (Hardware In Loop) - Data LineP16
DMM5IDebug Interface (Hardware In Loop) - Data LineL15
DMM6IDebug Interface (Hardware In Loop) - Data LineM16
DMM7IDebug Interface (Hardware In Loop) - Data LineJ15
DMM8IDebug Interface (Hardware In Loop) - Data LineD17
DMM9IDebug Interface (Hardware In Loop) - Data LineD16
DMM10IDebug Interface (Hardware In Loop) - Data LineE15
DMM11IDebug Interface (Hardware In Loop) - Data LineC18
DMM12IDebug Interface (Hardware In Loop) - Data LineB17
DMM13IDebug Interface (Hardware In Loop) - Data LineA17
DMM14IDebug Interface (Hardware In Loop) - Data LineC17
DMM_CLKIDebug Interface (Hardware In Loop) - ClockR15
DMM_SYNCIDebug Interface (Hardware In Loop) - SyncT17
DMM_MUX_INIDebug Interface (Hardware In Loop) Mux Select between DMM1 and DMM2 (Two Instances)A16,R17,R14
NDMM_ENODebug Interface (Hardware In Loop) Enable - Active Low SignalD15,E17
General-purpose I/OsMSS_GPIO_0IOGeneral-purpose I/OB15,P17,U15,A14
MSS_GPIO_1IOGeneral-purpose I/OA16,T18,U16,B13
MSS_GPIO_2IOGeneral-purpose I/OG15,N15,T16,V17,D11
MSS_GPIO_3IOGeneral-purpose I/OP16,T15
MSS_GPIO_4IOGeneral-purpose I/OU14,L15,V17
MSS_GPIO_5IOGeneral-purpose I/OT13,M16
MSS_GPIO_6IOGeneral-purpose I/OU12,J15
MSS_GPIO_7IOGeneral-purpose I/OR10,D17
MSS_GPIO_8IOGeneral-purpose I/OU11,T18,D16,V17,B16,B13
MSS_GPIO_9IOGeneral-purpose I/OV11,N15,E15,C16,D11
MSS_GPIO_10IOGeneral-purpose I/OT11,M16,C18,A15
MSS_GPIO_11IOGeneral-purpose I/OR12,J15,B17,B14
MSS_GPIO_12IOGeneral-purpose I/OV16,A17,B16
MSS_GPIO_13IOGeneral-purpose I/OB15,C17,C16
MSS_GPIO_14IOGeneral-purpose I/OE17,A15
MSS_GPIO_15IOGeneral-purpose I/OF16,B14
MSS_GPIO_16IOGeneral-purpose I/OA16
MSS_GPIO_17IOGeneral-purpose I/OC12,C17,U8
MSS_GPIO_18IOGeneral-purpose I/OC14,A17,R8
MSS_GPIO_19IOGeneral-purpose I/OB17,U9
MSS_GPIO_20IOGeneral-purpose I/OC18,R6
MSS_GPIO_21IOGeneral-purpose I/OV12,E15,T7
MSS_GPIO_22IOGeneral-purpose I/OU13,D16,U4
MSS_GPIO_23IOGeneral-purpose I/OD13,D17,U6
MSS_GPIO_24IOGeneral-purpose I/OD15,J15,U5
MSS_GPIO_25IOGeneral-purpose I/OR15,M16,U7
MSS_GPIO_26IOGeneral-purpose I/OG15,L15,V3
MSS_GPIO_27IOGeneral-purpose I/OT17,P16,T9
MSS_GPIO_28IOGeneral-purpose I/OR17,N15,U10
MSS_GPIO_29IOGeneral-purpose I/OR14,T18,V5,D11
MSS_GPIO_30IOGeneral-purpose I/OP17,V4,T5,B13
MSS_GPIO_31IOGeneral-purpose I/OU17,V6,R4,A14
UART (DSS) DSS_UARTA_TXIODebug UART Transmit [DSP]U13,R10,J15,B16,A15,A14
DSS_UARTA_RXIODebug UART Receive [DSP]D13,R17,C16,B14
Chirp/Frame signalsADC_VALIDOWhen high, indicating valid ADC samplesV16,T11,R12,R17
CHIRP_STARTOPulse signal indicating the start of each chirpG15,T17
CHIRP_ENDOPulse signal indicating the end of each chirp G15,T17
FRAME_STARTOPulse signal indicating the start of each frameR15,G15,T17
LVDS_VALIDLVDS_VALIDOWhen high, indicating valid LVDS data A16,R15,G15,T17,R14,E17,A14
External clock outMCU_CLKOUTOProgrammable clock given out to external MCU or the processorR15,B13
PMIC_CLKOUTOOutput Clock from the device for PMICB15,G15,T17,D11
System SynchronizationSYNC_INILow frequency Synchronization signal inputR17
SYNC_OUTOLow Frequency Synchronization Signal outputA16,G15,R17,R14
Clock OutputOBS_CLKOUTOObservation Clock OutputR15,T17
RCOSC_CLKOInternal RCOSC Clock OutputR14
Reference ClockXREF_CLK0IExternal reference input clock 0B13
XREF_CLK1IExternal reference input clock 1D11
JTAGTCKIJTAG Test ClockC12
TMSIOJTAG Test Mode SignalC14
TDIIJTAG Test Data InputD13
TDOOJTAG Test Data OutputD15
UART (BSS)BSS_UARTA_TXODebug UART Transmit [Radar Block]A16,T13,U14,C14,D15,F16,E17,M16
BSS_UARTA_RXIDebug UART Receive [Radar Block]C12,R15
ResetWARM_RESETIOOpen drain fail safe warm reset signal. Can be driven from PMIC for diagnostic or can be used as status signal that the device is going through reset.B12
SafetyNERROR_OUTOOpen drain fail safe output signal. Connected to PMIC/Processor/MCU to indicate that some severe criticality fault has happened. Recovery would be through reset.C11
Sense On powerSOP[0]IThe SOP pins are driven externally (weak drive) and the mmWave device senses the state of these pins during bootup to decide the bootup mode. After boot the same pins have other functionality.
  • [SOP2 SOP1 SOP0] = [0 0 1] -> Functional QSPI load mode
  • [SOP2 SOP1 SOP0] = [1 0 1] -> UART load mode
  • [SOP2 SOP1 SOP0] = [0 1 1] -> debug and development mode
The following configuration of SOP pins help decide the reference crystal frequency
  • [SOP4 SOP3] = [0 0] -> 40 MHz
D15
SOP[1]IR14
SOP[2]IT17
SOP[3]IA14
SOP[4]IC16
CSI2 RXCSI2_RX0M0ICSI2.0 Receiver #1, Negative Polarity, Lane 0N18
CSI2_RX0P0ICSI2.0 Receiver #1, Positive Polarity, Lane 0N17
CSI2_RX0CLKMICSI2.0 Receiver #1, Clock Input, Negative PolarityL18
CSI2_RX0CLKPICSI2.0 Receiver #1, Clock Input, Positive PolarityL17
CSI2_RX0M1ICSI2.0 Receiver #1, Negative Polarity Lane 1M18
CSI2_RX0P1ICSI2.0 Receiver #1, Positive Polarity Lane 1M17
Aurora LVDSLVDS_TXM0OLVDS/Aurora Transmitter, Data Output, Lane 0F18
LVDS_TXP0OF17
LVDS_TXM2_CLKMOLVDS Clock, Aurora Data output - Lane 2G18
LVDS_TXP2_CLKPOG17
LVDS_TXM3_FRCLKMOLVDS Frame Clock, Aurora Data Output - Lane 3H18
LVDS_TXP3_FRCLKPOH17
LVDS_TXM1OLVDS/Aurora Transmitter, Data Output, Lane 1J18
LVDS_TXP1OJ17
(1) In order to meet SPI timings, it is recommended to use MSS_MIBSPIB_CLK = T13 with MSS_MIBSPIB_MOSI = V12 and MSS_MIBSPIB_MISO = U13. The same applies for the other MSS_MIBSPIB_CLK = R10 as well i.e. with MSS_MIBSPIB_MOSI = V11 and MSS_MIBSPIB_MISO = U11