SWRS313A July   2023  – June 2024 IWRL1432

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configurations and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Signal Descriptions
      1.      11
      2.      12
      3.      13
      4.      14
      5.      15
      6.      16
      7.      17
      8.      18
      9.      19
      10.      20
      11.      21
      12.      22
      13.      23
      14.      24
      15.      25
      16.      26
    3.     27
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.5.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.5.2 Hardware Requirements
      3. 7.5.3 Impact to Your Hardware Warranty
    6. 7.6  Power Supply Specifications
      1. 7.6.1 Power Optimized 3.3V I/O Topology
      2. 7.6.2 BOM Optimized 3.3V I/O Topology
      3. 7.6.3 Power Optimized 1.8V I/O Topology
      4. 7.6.4 BOM Optimized 1.8V I/O Topology
      5. 7.6.5 System Topologies
        1. 7.6.5.1 Power Topologies
          1. 7.6.5.1.1 BOM Optimized Mode
          2. 7.6.5.1.2 Power Optimized Mode
      6. 7.6.6 Internal LDO output decoupling capacitor and layout conditions for BOM optimized topology
        1. 7.6.6.1 Single-capacitor rail
          1. 7.6.6.1.1 1.2V Digital LDO
        2. 7.6.6.2 Two-capacitor rail
          1. 7.6.6.2.1 1.2V RF LDO
          2. 7.6.6.2.2 1.2V SRAM LDO
          3. 7.6.6.2.3 1.0V RF LDO
      7. 7.6.7 Noise and Ripple Specifications
    7. 7.7  Power Save Modes
      1. 7.7.1 Typical Power Consumption Numbers
    8. 7.8  Peak Current Requirement per Voltage Rail
    9. 7.9  RF Specification
    10. 7.10 Supported Front End features
    11. 7.11 CPU Specifications
    12. 7.12 Thermal Resistance Characteristics
    13. 7.13 Timing and Switching Characteristics
      1. 7.13.1  Power Supply Sequencing and Reset Timing
      2. 7.13.2  Synchronized Frame Triggering
      3. 7.13.3  Input Clocks and Oscillators
        1. 7.13.3.1 Clock Specifications
      4. 7.13.4  MultiChannel buffered / Standard Serial Peripheral Interface (McSPI)
        1. 7.13.4.1 McSPI Features
        2. 7.13.4.2 SPI Timing Conditions
        3. 7.13.4.3 SPI—Controller Mode
          1. 7.13.4.3.1 Timing and Switching Requirements for SPI - Controller Mode
          2. 7.13.4.3.2 Timing and Switching Characteristics for SPI Output Timings—Controller Mode
        4. 7.13.4.4 SPI—Peripheral Mode
          1. 7.13.4.4.1 Timing and Switching Requirements for SPI - Peripheral Mode
          2. 7.13.4.4.2 Timing and Switching Characteristics for SPI Output Timings—Secondary Mode
      5. 7.13.5  RDIF Interface Configuration
        1. 7.13.5.1 RDIF Interface Timings
        2. 7.13.5.2 RDIF Data Format
      6. 7.13.6  General-Purpose Input/Output
        1. 7.13.6.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      7. 7.13.7  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 7.13.7.1 Dynamic Characteristics for the CANx TX and RX Pins
      8. 7.13.8  Serial Communication Interface (SCI)
        1. 7.13.8.1 SCI Timing Requirements
      9. 7.13.9  Inter-Integrated Circuit Interface (I2C)
        1. 7.13.9.1 I2C Timing Requirements
      10. 7.13.10 Quad Serial Peripheral Interface (QSPI)
        1. 7.13.10.1 QSPI Timing Conditions
        2. 7.13.10.2 Timing Requirements for QSPI Input (Read) Timings
        3. 7.13.10.3 QSPI Switching Characteristics
      11. 7.13.11 JTAG Interface
        1. 7.13.11.1 JTAG Timing Conditions
        2. 7.13.11.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 7.13.11.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
      2. 8.3.2 Clock Subsystem
      3. 8.3.3 Transmit Subsystem
      4. 8.3.4 Receive Subsystem
      5. 8.3.5 Processor Subsystem
      6. 8.3.6 Host Interface
      7. 8.3.7 Application Subsystem
      8. 8.3.8 Hardware Accelerator (HWA1.2) Features
        1. 8.3.8.1 Hardware Accelerator Feature Differences Between HWA1.1 and HWA1.2
    4. 8.4 Other Subsystems
      1. 8.4.1 GPADC Channels (Service) for User Application
      2. 8.4.2 GPADC Parameters
    5. 8.5 Memory Partitioning Options
    6. 8.6 Boot Modes
  10. 9 Monitoring and Diagnostics
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation Support
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • AMF|102
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Table 6-17 Pin Muxing Table
BALL NUMBER(1) BALL NAME(2) SIGNAL NAME(3) PIN CNTL REGISTER(4) PIN CNTL REGISTER ADDRESS(5)(11) MODE(6) TYPE(7) BALL STATE DURING RESET(9) BALL STATE AFTER RESET(10) PULL UP/DOWN TYPE(8)
H10 GPIO_2 GPIO_2 PADAL_CFG_REG 0x5A00 002C 0 IO Off / Off / Off Off / Off / Off PU/PD
LIN_RX 1 I
WARM_RESET_OUT 2 O
I2C_SDA 3 IO
SPIA_CS1_N 4 IO
WU_REQIN 5 I
RTC_CLK_IN 6 I
MDO_D0 7 O
J10 GPIO_5 GPIO_5 PADAV_CFG_REG 0x5A00 0054 0 IO Off / Off / Off Off / Off / Off PU/PD
SYNC_IN 1 I
LIN_RX 2 I
EPWMB 3 O
EPWM_SYNC_IN 4 I
MDO_D3 5 O
M10 HOST_CLK_REQ HOST_CLK_REQ PADAX_CFG_REG 0x5A00 005C 0 O Off / Off / Off Off / SS / Off PU/PD
GPIO_7 1 IO
MCU_CLKOUT 2 O
LIN_TX 3 O
WU_REQIN 4 I
SPIB_MISO 5 IO
I2C_SCL 6 IO
MDO_D3 8 O
MDO_FRM_CLK 9 O
K11 NERROR_OUT NERROR_OUT PADAU_CFG_REG 0x5A00 0050 0 O Off / Off / Off Off / Off / Off PU/PD
GPIO_4 1 IO
SYNC_IN 2 I
SPIB_CS0_N 3 IO
WU_REQIN 4 I
RTC_CLK_IN 5 I
MCU_CLKOUT 6 O
MDO_D3 7 O
H11 PMIC_CLKOUT SOP[1] PADAK_CFG_REG 0x5A00 0028 During Power-up I Off / Off / Off Off / Off / Off PU/PD
PMIC_CLKOUT 0 O
LIN_TX 1 O
SPIA_CS1_N 2 IO
MDO_FRM_CLK 3 O
B11 QSPI[0] QSPI[0] PADAC_CFG_REG 0x5A00 0008 0 IO Off / Off / Off Off / Off / Off PU/PD
SPIB_MOSI 1 IO
MDO_D0 2 O
B8 QSPI[1] QSPI[1] PADAD_CFG_REG 0x5A00 000C 0 I Off / Off / Off Off / Off / Off PU/PD
SPIB_MISO 1 IO
RTC_CLK_IN 2 I
MDO_D3 3 O
B10 QSPI[2] QSPI[2] PADAE_CFG_REG 0x5A00 0010 0 I Off / Off / Off Off / Off / Off PU/PD
I2C_SCL 1 IO
WU_REQIN 2 I
MDO_D1 3 O
B9 QSPI[3] QSPI[3] PADAF_CFG_REG 0x5A00 0014 0 I Off / Off / Off Off / Off / Off PU/PD
I2C_SDA 1 IO
SYNC_IN 2 I
MDO_D2 3 O
A11 QSPI_CLK QSPI_CLK PADAA_CFG_REG 0x5A00 0000 0 IO Off / Off / Off Off / Off / Off PU/PD
SPIB_CLK 1 IO
MDO_CLK 2 O
A10 QSPI_CS QSPI_CS PADAB_CFG_REG 0x5A00 0004 0 O Off / Off / Off Off / Off / Off PU/PD
SPIB_CS0_N 1 IO
MDO_FRM_CLK 2 O
F11 RS232_RX RS232_RX PADAP_CFG_REG 0x5A00 003C 0 I Off / Off / Up On / Off / Up PU/PD
I2C_SDA 1 IO
UARTB_RX 2 I
LIN_RX 3 I
MDO_D2 4 O
SPIB_MISO 5 IO
E10 RS232_TX RS232_TX PADAO_CFG_REG 0x5A00 0038 0 O Off / Off / Off Off / SS / Off PU/PD
I2C_SCL 1 IO
UARTB_TX 2 O
LIN_TX 3 O
EPWM_SYNC_IN 4 I
MDO_D1 5 O
SPIB_CS1_N 6 IO
D10 SPIA_CLK SPIA_CLK PADAG_CFG_REG 0x5A00 0018 0 IO Off / Off / Off Off / Off / Off PU/PD
EPWMB 1 O
I2C_SCL 2 IO
SPIB_CLK 3 IO
MDO_CLK 4 O
D11 SPIA_CS0_N SPIA_CS0_N PADAH_CFG_REG 0x5A00 001C 0 IO Off / Off / Off Off / Off / Off PU/PD
EPWMA 1 O
I2C_SDA 2 IO
SPIB_CS0_N 3 IO
MDO_D3 4 O
C11 SPIA_MISO SPIA_MISO PADAJ_CFG_REG 0x5A00 0024 0 IO Off / Off / Off Off / Off / Off PU/PD
GPIO_1 1 IO
EPWMA 2 O
SPIB_MISO 3 IO
MDO_D2 4 O
B12 SPIA_MOSI SPIA_MOSI PADAI_CFG_REG 0x5A00 0020 0 IO Off / Off / Off Off / Off / Off PU/PD
GPIO_0 1 IO
EPWMB 2 O
SPIB_MOSI 3 IO
MDO_D1 4 O
C12 TCK TCK PADAT_CFG_REG 0x5A00 004C 0 I Off / Off / Down On / Off / Down PU/PD
EPWMB 1 O
SPIB_CS1_N 2 IO
SPIB_MOSI 3 IO
MDO_D0 4 O
G11 TDI TDI PADAR_CFG_REG 0x5A00 0044 0 I Off / Off / Down On / Off / Down PU/PD
EPWMA 1 O
SPIB_CS0_N 2 IO
E11 TDO SOP[0] PADAS_CFG_REG 0x5A00 0048 During Power-up I Off / Off / Off Off / SS / Off PU/PD
TDO 0 O
MDO_FRM_CLK 1 O
E12 TMS TMS PADAQ_CFG_REG 0x5A00 0040 0 I Off / Off / Up On / Off / Up PU/PD
WARM_RESET_OUT 1 O
SPIA_CS1_N 2 IO
SYNC_IN 3 I
SPIB_MISO 4 IO
SPIB_CLK 5 IO
RTC_CLK_IN 6 I
EPWM_SYNC_IN 7 I
EPWM_SYNC_OUT 8 O
L11 UARTA_RTS UARTA_RTS PADAW_CFG_REG 0x5A00 0058 0 O Off / Off / Off Off / Off / Off PU/PD
GPIO_6 1 IO
LIN_TX 2 O
SPIB_CLK 3 IO
WU_REQIN 4 I
EPWMA 5 O
RTC_CLK_IN 6 I
MDO_CLK 7 O
J11 UARTA_RX UARTA_RX PADAM_CFG_REG 0x5A00 0030 0 I Off / Off / Off Off / Off / Off PU/PD
GPIO_3 1 IO
LIN_RX 2 I
CAN_FD_RX 3 I
SYNC_IN 4 I
UARTB_RX 5 I
I2C_SDA 6 IO
MDO_D1 7 O
L12 UARTA_TX UARTA_TX PADAN_CFG_REG 0x5A00 0034 0 O Off / Off / Off Off / Off / Off PU/PD
LIN_TX 1 O
CAN_FD_TX 2 O
SPIB_MOSI 3 IO
WU_REQIN 4 I
UARTB_TX 5 O
I2C_SCL 6 IO
MDO_D2 7 O
(1) BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom.
(2) BALL NAME: Mechanical name from package device (name is taken from muxmode 0).
(3) SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0).
(4) PINCNTL_REGISTER: APPSS Register name for PinMux Control
(5) PINCNTL ADDRESS: APPSS Address for PinMux Control
(6) MODE: Multiplexing mode number: value written to PinMux Cntl register to select specific Signal name for this Ball number. Mode column has bit range value.
(7) TYPE: Signal type and direction:
  • I = Input
  • O = Output
  • IO = Input or Output
(8) PULL UP/DOWN TYPE: indicates the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software.
  • Pull Up: Internal pullup
  • Pull Down: Internal pulldown
  • An empty box means No pull.
(9) BALL STATE DURING RST: State of Ball during reset in the format of RX/TX/Pull Status
  • RX (Input buffer)
    • Off: The input buffer is disabled.
    • On: The input buffer is enabled.
  • TX (Output buffer)
    • Off: The output buffer is disabled.
    • Low: The output buffer is enabled and drives VOL.
  • Pull Status (Internal pull resistors)
    • Off: Internal pull resistors are turned off.
    • Up: Internal pull-up resistor is turned on.
    • Down: Internal pull-down resistor is turned on.
    • NA: No internal pull resistor.
  • An empty box, or "-" means Not Applicable.
(10) BALL STATE AFTER RST: State of Ball after reset in the format of RX/TX/Pull Status
  • RX (Input buffer)
    • Off: The input buffer is disabled.
    • On: The input buffer is enabled.
  • TX (Output buffer)
    • Off: The output buffer is disabled.
    • SS: The subsystem selected with MUXMODE determines the output buffer state.
  • Pull status (Internal pull resistors)
    • Off: Internal pull resistors are turned off.
    • Up: Internal pull-up resistor is turned on.
    • Down: Internal pull-down resistor is turned on.
    • NA: No internal pull resistor.
  • An empty box, NA, or "-" means Not Applicable.
(11) Pin Mux Control Value maps to lower 4 bits of register.