SWRS313A July   2023  – June 2024 IWRL1432

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configurations and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Signal Descriptions
      1.      11
      2.      12
      3.      13
      4.      14
      5.      15
      6.      16
      7.      17
      8.      18
      9.      19
      10.      20
      11.      21
      12.      22
      13.      23
      14.      24
      15.      25
      16.      26
    3.     27
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.5.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.5.2 Hardware Requirements
      3. 7.5.3 Impact to Your Hardware Warranty
    6. 7.6  Power Supply Specifications
      1. 7.6.1 Power Optimized 3.3V I/O Topology
      2. 7.6.2 BOM Optimized 3.3V I/O Topology
      3. 7.6.3 Power Optimized 1.8V I/O Topology
      4. 7.6.4 BOM Optimized 1.8V I/O Topology
      5. 7.6.5 System Topologies
        1. 7.6.5.1 Power Topologies
          1. 7.6.5.1.1 BOM Optimized Mode
          2. 7.6.5.1.2 Power Optimized Mode
      6. 7.6.6 Internal LDO output decoupling capacitor and layout conditions for BOM optimized topology
        1. 7.6.6.1 Single-capacitor rail
          1. 7.6.6.1.1 1.2V Digital LDO
        2. 7.6.6.2 Two-capacitor rail
          1. 7.6.6.2.1 1.2V RF LDO
          2. 7.6.6.2.2 1.2V SRAM LDO
          3. 7.6.6.2.3 1.0V RF LDO
      7. 7.6.7 Noise and Ripple Specifications
    7. 7.7  Power Save Modes
      1. 7.7.1 Typical Power Consumption Numbers
    8. 7.8  Peak Current Requirement per Voltage Rail
    9. 7.9  RF Specification
    10. 7.10 Supported Front End features
    11. 7.11 CPU Specifications
    12. 7.12 Thermal Resistance Characteristics
    13. 7.13 Timing and Switching Characteristics
      1. 7.13.1  Power Supply Sequencing and Reset Timing
      2. 7.13.2  Synchronized Frame Triggering
      3. 7.13.3  Input Clocks and Oscillators
        1. 7.13.3.1 Clock Specifications
      4. 7.13.4  MultiChannel buffered / Standard Serial Peripheral Interface (McSPI)
        1. 7.13.4.1 McSPI Features
        2. 7.13.4.2 SPI Timing Conditions
        3. 7.13.4.3 SPI—Controller Mode
          1. 7.13.4.3.1 Timing and Switching Requirements for SPI - Controller Mode
          2. 7.13.4.3.2 Timing and Switching Characteristics for SPI Output Timings—Controller Mode
        4. 7.13.4.4 SPI—Peripheral Mode
          1. 7.13.4.4.1 Timing and Switching Requirements for SPI - Peripheral Mode
          2. 7.13.4.4.2 Timing and Switching Characteristics for SPI Output Timings—Secondary Mode
      5. 7.13.5  RDIF Interface Configuration
        1. 7.13.5.1 RDIF Interface Timings
        2. 7.13.5.2 RDIF Data Format
      6. 7.13.6  General-Purpose Input/Output
        1. 7.13.6.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      7. 7.13.7  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 7.13.7.1 Dynamic Characteristics for the CANx TX and RX Pins
      8. 7.13.8  Serial Communication Interface (SCI)
        1. 7.13.8.1 SCI Timing Requirements
      9. 7.13.9  Inter-Integrated Circuit Interface (I2C)
        1. 7.13.9.1 I2C Timing Requirements
      10. 7.13.10 Quad Serial Peripheral Interface (QSPI)
        1. 7.13.10.1 QSPI Timing Conditions
        2. 7.13.10.2 Timing Requirements for QSPI Input (Read) Timings
        3. 7.13.10.3 QSPI Switching Characteristics
      11. 7.13.11 JTAG Interface
        1. 7.13.11.1 JTAG Timing Conditions
        2. 7.13.11.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 7.13.11.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
      2. 8.3.2 Clock Subsystem
      3. 8.3.3 Transmit Subsystem
      4. 8.3.4 Receive Subsystem
      5. 8.3.5 Processor Subsystem
      6. 8.3.6 Host Interface
      7. 8.3.7 Application Subsystem
      8. 8.3.8 Hardware Accelerator (HWA1.2) Features
        1. 8.3.8.1 Hardware Accelerator Feature Differences Between HWA1.1 and HWA1.2
    4. 8.4 Other Subsystems
      1. 8.4.1 GPADC Channels (Service) for User Application
      2. 8.4.2 GPADC Parameters
    5. 8.5 Memory Partitioning Options
    6. 8.6 Boot Modes
  10. 9 Monitoring and Diagnostics
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation Support
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • AMF|102
Thermal pad, mechanical data (Package|Pins)
Orderable Information
7.13.4.3.1 Timing and Switching Requirements for SPI - Controller Mode

Table 7-21 and Table 7-21 present timing requirements for SPI - Controller Mode.

Table 7-21 SPI Timing Requirements - Controller Mode
NO.(1)(8)MODEMINMAXUNIT
SM4tsu(MISO-SPICLK)Setup time, SPI_D[x] valid before SPI_CLK active edge (1)

5

ns
SM5th(SPICLK-MISO)Hold time, SPI_D[x] valid after SPI_CLK active edge (1)3ns
Table 7-22 SPI Switching Characteristics - Controller Mode
NO.(1)(8)MODEMINMAXUNIT
SM1tc(SPICLK)Cycle time, SPI_CLK (1)(2)24.6(3)ns
SM2tw(SPICLKL)Typical Pulse duration, SPI_CLK low (1)-1 + 0.5P(3)(4)ns
SM3tw(SPICLKH)Typical Pulse duration, SPI_CLK high (1)-1 + 0.5P(4)ns
SM6td(SPICLK-SIMO)Delay time, SPI_CLK active edge to SPI_D[x] transition (1)-2

5

ns
SM7tsk(CS-SIMO)Delay time, SPI_CS[x] active to SPI_D[x] transition

5

ns
SM8td(SPICLK-CS)Delay time, SPI_CS[x] active to SPI_CLK first edgeController_PHA0_POL0; Controller_PHA0_POL1;(5)-4 + B(6)ns
Controller_PHA1_POL0; Controller_PHA1_POL1;(5)-4 + A(7)ns
SM9td(SPICLK-CS)Delay time, SPI_CLK last edge to SPI_CS[x] inactiveController_PHA0_POL0; Controller_PHA0_POL1;(5)-4 + A(7)ns
Controller_PHA1_POL0; Controller_PHA1_POL1; (5)-4 + B(6)ns

SM11

Cb

Capacitive load for each bus line

3

15

pF

This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are being used to drive output data and capture input data
(1) P = This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are being used to drive output data and capture input data
(2) Related to the SPI_CLK maximum frequency
(3) 20 ns cycle time = 50 MHz
(4) P = SPICLK period
(5) SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register
(6) B = (TCS + .5) × TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even >= 2.
(7) When P = 20.8 ns, A = (TCS + 1) × TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.
When P > 20.8 ns, A = (TCS + 0.5) × Fratio × TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.
(8) The IO timings provided in this section are applicable for all combinations of signals for SPI1 and SPI2. However, the timings are only valid for SPI3 and SPI4 if signals within a single IOSET are used. The IOSETs are defined in the following tables.
Note:

Supported frequency of Radar SPI Peripheral mode is 40MHz in full cycle and 20MHz in Half cycle mode.