For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:
- Reduce parasitic coupling by running the input
traces as far away from the supply or output
traces as possible. If these traces cannot be kept
separate, crossing the sensitive trace
perpendicular is much better as opposed to in
parallel with the noisy trace.
- Place the external components as close to the
device as possible.
- Keep the length of input traces as short
as possible. Always remember that the input traces are the most sensitive part of the
circuit.
- Keep high impedance input
signals away from noisy traces.
- Make sure supply voltages
are adequately filtered.
- Minimize distance between source-connected and drain-connected components to
the JFE2140.
- Consider a driven, low-impedance guard ring
around the critical gate traces. A guard ring can significantly reduce leakage
currents from nearby traces that are at different potentials.
- Clean the PCB following board assembly for best
performance.
- Any precision integrated circuit can experience
performance shifts resulting from moisture ingress
into the plastic package. Following any aqueous
PCB cleaning process, bake the PCB assembly to
remove moisture introduced into the device
packaging during the cleaning process. A low
temperature, post-cleaning bake at 85°C for 30
minutes is sufficient for most circumstances.