SLPS730B august   2021  – august 2023 JFE2140

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 AC Measurement Configurations
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Precision Matching
      2. 8.3.2 Ultra-Low Noise
      3. 8.3.3 Low Gate Current
      4. 8.3.4 Input Protection
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Protection Diodes
      2. 9.1.2 Cascode Configuration
      3. 9.1.3 Common-Source Amplifier
      4. 9.1.4 Composite Amplifiers
    2. 9.2 Typical Applications
      1. 9.2.1 Low-Noise, Low-Power, High-Input-Impedance Composite Amplifier
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Differential Front-End Design
        1. 9.2.2.1 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 PSpice® for TI
        2. 10.1.1.2 TINA-TI™ Simulation Software (Free Download)
        3. 10.1.1.3 TI Reference Designs
        4. 10.1.1.4 Filter Design Tool
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.1.3 Common-Source Amplifier

The common-source amplifier is a commonly used open-loop gain stage for JFET amplifiers, the basic circuit is shown in Figure 9-3.

GUID-20210811-SS0I-HQ34-CKFV-K44WNRV36BQN-low.gif Figure 9-3 Common-Source Amplifier

The equation for gain of the circuit in Figure 9-3 is shown in Equation 1.

Equation 1. VOUTVIN= - gm*RD1+gm*RS

Generally, higher gain results in improved noise performance. Gain increases as the bias current is increased as a result of increasing gm (see Figure 6-4). As a result, the input-referred noise decreases as bias current is increased (see Figure 6-14). Any JFET design must make a tradeoff between current consumption and noise performance. The JFE2140, however, delivers significantly lower noise performance than most operational amplifiers at the same current consumption. The bias current (IDS) is set by the value of the source resistor, RS, and the threshold voltage, VT, of the JFE2140. For JFETs, this threshold voltage is equivalent to the gate-to-source cutoff voltage, VGSC. A graph showing nominal IDS vs RS is shown in Figure 9-4.

GUID-20210811-SS0I-MKGF-LP8T-H5DB4KJSL8C4-low.png Figure 9-4 Drain-to-Source Current vs RS, VDS = 5 V

The bias current varies according to the resistor and threshold voltage tolerances. Additionally, thermal noise associated with RS couples directly into the gain of the circuit, degrading the overall noise performance. To improve the circuit in Figure 9-5, use a current-source biasing scheme. Current-source biasing removes the JFET threshold variation from the biasing scheme, and allows for lower-value filtering capacitance (CS) for equivalent filtering due to the high output impedance of current sources.

GUID-20210812-SS0I-PX1P-SRBV-SWCTHZ0Z5WJ9-low.gif Figure 9-5 Common-Source Amplifier With Current-Source Biasing