SLPS730B august   2021  – august 2023 JFE2140

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 AC Measurement Configurations
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Precision Matching
      2. 8.3.2 Ultra-Low Noise
      3. 8.3.3 Low Gate Current
      4. 8.3.4 Input Protection
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Protection Diodes
      2. 9.1.2 Cascode Configuration
      3. 9.1.3 Common-Source Amplifier
      4. 9.1.4 Composite Amplifiers
    2. 9.2 Typical Applications
      1. 9.2.1 Low-Noise, Low-Power, High-Input-Impedance Composite Amplifier
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Differential Front-End Design
        1. 9.2.2.1 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 PSpice® for TI
        2. 10.1.1.2 TINA-TI™ Simulation Software (Free Download)
        3. 10.1.1.3 TI Reference Designs
        4. 10.1.1.4 Filter Design Tool
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

at TA = 25°C, IDS = 2 mA, VDS = 10 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
NOISE
en Input-referred noise IDS = 100 µA  f = 1 kHz 2.5 nV/√Hz
f = 10 Hz 5.4
f = 0.1 Hz to 10 Hz 0.26 µVPP
IDS = 2 mA  f = 1 kHz 1.1 nV/√Hz
f = 10 Hz 2.4
f = 0.1 Hz to 10 Hz 0.12 µVPP
ei Input current noise, each input f = 1 kHz, IDS = 2 mA, VDS = 5 V 1.6 fA/√Hz
INPUT CURRENT
IG Input gate current VDS = 2 V, VVCH = 5 V, VVCL = –5 V 1 ±10 pA
VDS = 0 V, 
VGS = –30 V		 0.2 ±60
TA = –40°C to +85°C 0.85 nA
TA = –40°C to +125°C 9
INPUT VOLTAGE
VGSS Gate-to-source breakdown voltage VDS = 0 V, IG = –100 µA −40 V
VGSC Gate-to-source cutoff voltage VDS = 10 V, IDS = 0.1 µA −1.5 −1.15 −0.9 V
VGS Gate-to-source voltage IDS = 100 µA −1.3 −0.85 −0.7 V
IDS = 2 mA −1.1 −0.6 −0.5
ΔVGS Differential VGS mismatch IDS = 2 mA 1 4 mV
TA = –40°C to +125°C 1.1 4.2
Differential VGS mismatch drift TA = –40°C to +125°C 1.7 ±10 µV/°C
INPUT IMPEDANCE
RIN Gate input resistance VGS = –30 V to –1 V,  VDS = 0 V 1 TΩ
CISS Input capacitance VDS = 0 V 17 pF
VDS = 5 V 13
OUTPUT
IDSS Drain-to-source saturation current VGS = 0 V  12 18 23 mA
TA = –40°C to +125°C 10 28
Drain-to-source saturation current ratio VGS = 0 V, IDSS1 / IDSS2 0.95 1 1.05
Transconductance  IDS = 100 µA 2.1 mS
IDS = 2 mA 10
GFS Full conduction transconductance VGS = 0 V 24 30 mS
VDSS Drain-to-source breakdown voltage IDS = 100 µA 40 43 V
COSS Output capacitance IDS = 2 mA 4.5 pF