SNOSCZ6 April   2016 LDC1312-Q1 , LDC1314-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description Continued
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Switching Characteristics - I2C
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Clocking Architecture
      2. 8.3.2 Multi-Channel and Single Channel Operation
      3. 8.3.3 Current Drive Control Registers
      4. 8.3.4 Device Status Registers
      5. 8.3.5 Input Deglitch Filter
    4. 8.4 Device Functional Modes
      1. 8.4.1 Startup Mode
      2. 8.4.2 Normal (Conversion) Mode
      3. 8.4.3 Sleep Mode
      4. 8.4.4 Shutdown Mode
        1. 8.4.4.1 Reset
    5. 8.5 Programming
      1. 8.5.1 I2C Interface Specifications
    6. 8.6 Register Maps
      1. 8.6.1  Register List
      2. 8.6.2  Address 0x00, DATA_CH0
      3. 8.6.3  Address 0x02, DATA_CH1
      4. 8.6.4  Address 0x04, DATA_CH2 (LDC1314 only)
      5. 8.6.5  Address 0x06, DATA_CH3 (LDC1314 only)
      6. 8.6.6  Address 0x08, RCOUNT_CH0
      7. 8.6.7  Address 0x09, RCOUNT_CH1
      8. 8.6.8  Address 0x0A, RCOUNT_CH2 (LDC1314 only)
      9. 8.6.9  Address 0x0B, RCOUNT_CH3 (LDC1314 only)
      10. 8.6.10 Address 0x0C, OFFSET_CH0
      11. 8.6.11 Address 0x0D, OFFSET_CH1
      12. 8.6.12 Address 0x0E, OFFSET_CH2 (LDC1314 only)
      13. 8.6.13 Address 0x0F, OFFSET_CH3 (LDC1314 only)
      14. 8.6.14 Address 0x10, SETTLECOUNT_CH0
      15. 8.6.15 Address 0x11, SETTLECOUNT_CH1
      16. 8.6.16 Address 0x12, SETTLECOUNT_CH2 (LDC1314 only)
      17. 8.6.17 Address 0x13, SETTLECOUNT_CH3 (LDC1314 only)
      18. 8.6.18 Address 0x14, CLOCK_DIVIDERS_CH0
      19. 8.6.19 Address 0x15, CLOCK_DIVIDERS_CH1
      20. 8.6.20 Address 0x16, CLOCK_DIVIDERS_CH2 (LDC1314 only)
      21. 8.6.21 Address 0x17, CLOCK_DIVIDERS_CH3 (LDC1314 only)
      22. 8.6.22 Address 0x18, STATUS
      23. 8.6.23 Address 0x19, ERROR_CONFIG
      24. 8.6.24 Address 0x1A, CONFIG
      25. 8.6.25 Address 0x1B, MUX_CONFIG
      26. 8.6.26 Address 0x1C, RESET_DEV
      27. 8.6.27 Address 0x1E, DRIVE_CURRENT_CH0
      28. 8.6.28 Address 0x1F, DRIVE_CURRENT_CH1
      29. 8.6.29 Address 0x20, DRIVE_CURRENT_CH2 (LDC1314 only)
      30. 8.6.30 Address 0x21, DRIVE_CURRENT_CH3 (LDC1314 only)
      31. 8.6.31 Address 0x7E, MANUFACTURER_ID
      32. 8.6.32 Address 0x7F, DEVICE_ID
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Theory of Operation
        1. 9.1.1.1 Conductive Objects in an EM Field
        2. 9.1.1.2 L-C Resonators
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Recommended Initial Register Configuration Values
        2. 9.2.2.2 Inductor Self-Resonant Frequency
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Related Links
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

Conductive objects brought in contact with an AC electromagnetic (EM) field will induce field changes that can be detected using a sensor such as an inductor. Conveniently, an inductor, along with a capacitor, can be used to construct an L-C resonator, also known as an L-C tank, which can be used to produce an EM field. In the case of an L-C tank, the effect of the field disturbance is an apparent shift in the inductance of the sensor, which can be observed as a shift in the resonant frequency. Using this principle, the LDC1312/1314 is an inductance-to-digital converter (LDC) that measures the oscillation frequency of an LC resonator. The device outputs a digital value that is proportional to frequency. This frequency measurement can be converted to an equivalent inductance.

8.2 Functional Block Diagram

LDC1312-Q1 LDC1314-Q1 bd_LDC1x12_LDC1x14_snoscy9.gif Figure 10. Block Diagrams for the LDC1312 (Left) and LDC1314 (Right)

The LDC1312/LDC1314 is composed of front-end resonant circuit drivers, followed by a multiplexer that sequences through the active channels, connecting them to the core that measures and digitizes the sensor frequency (fSENSOR). The core uses a reference frequency (fREF) to measure the sensor frequency. fREF is derived from either an internal reference clock (oscillator), or an externally supplied clock. The digitized output for each channel is proportional to the ratio of fSENSOR/fREF. The I2C interface is used to support device configuration and to transmit the digitized frequency values to a host processor. The LDC can be placed in shutdown mode, saving current, using the SD pin. The INTB pin may be configured to notify the host of changes in system status.

8.3 Feature Description

8.3.1 Clocking Architecture

Figure 11 shows the clock dividers and multiplexers of the LDC.

LDC1312-Q1 LDC1314-Q1 clk_diag_LDC161x_snoscy9.gif Figure 11. Clocking Diagram

(1) LDC1314 only

In Figure 11, the key clocks are fIN, fREF, and fCLK. fCLK is selected from either the internal clock source or external clock source (CLKIN). The frequency measurement reference clock, fREF, is derived from the fCLK source. TI recommends that precision applications use an external master clock that offers the stability and accuracy requirements needed for the application. The internal oscillator may be used in applications that require low cost and do not require high precision. The fINx clock is derived from sensor frequency for a channel x, fSENSORx. fREFx and fINx must meet the requirements listed in Table 1, depending on whether fCLK (master clock) is the internal or external clock.

Table 1. Clock Configuration Requirements

MODE(1) CLKIN SOURCE VALID fREFx RANGE (MHz) VALID fINx RANGE SET CHx_FIN_DIVIDER to SET CHx_SETTLECOUNT to SET CHx_RCOUNT to
Multi-Channel Internal fREFx < 55 < fREFx /4 ≥ b0001 (2) > 3 > 8
External fREFx < 40
Single-Channel Either external or internal fREFx < 35
(1) Channels 2 and 3 are only available for LDC1314
(2) If fSENSOR ≥ 8.75 MHz, then CHx_FIN_DIVIDER must be ≥ 2

Table 2 shows the clock configuration registers for all channels.

Table 2. Clock Configuration Registers

CHANNEL(1) CLOCK REGISTER FIELD [ BIT(S) ] VALUE
All fCLK = Master Clock Source CONFIG, addr 0x1A REF_CLK_SRC [9] b0 = internal oscillator is used as the master clock
b1 = external clock source is used as the master clock
0 fREF0 CLOCK_DIVIDERS_CH0, addr 0x14 CH0_FREF_DIVIDER [9:0] fREF0 = fCLK / CH0_FREF_DIVIDER
1 fREF1 CLOCK_DIVIDERS_CH1, addr 0x15 CH1_FREF_DIVIDER [9:0] fREF1 = fCLK / CH1_FREF_DIVIDER
2 fREF2 CLOCK_DIVIDERS_CH2, addr 0x16 CH2_FREF_DIVIDER [9:0] fREF2 = fCLK / CH2_FREF_DIVIDER
3 fREF3 CLOCK_DIVIDERS_CH3, addr 0x17 CH3_FREF_DIVIDER [9:0] fREF3 = fCLK / CH3_FREF_DIVIDER
0 fIN0 CLOCK_DIVIDERS_CH0, addr 0x14 CH0_FIN_DIVIDER [15:12] fIN0 = fSENSOR0 / CH0_FIN_DIVIDER
1 fIN1 CLOCK_DIVIDERS_CH1, addr 0x15 CH1_FIN_DIVIDER [15:12] fIN1 = fSENSOR1 / CH1_FIN_DIVIDER
2 fIN2 CLOCK_DIVIDERS_CH2, addr 0x16 CH2_FIN_DIVIDER [15:12] fIN2 = fSENSOR2 / CH2_FIN_DIVIDER
3 fIN3 CLOCK_DIVIDERS_CH3, addr 0x17 CH3_FIN_DIVIDER [15:12] fIN3 = fSENSOR3 / CH3_FIN_DIVIDER
(1) Channels 2 and 3 are only available for LDC1314

8.3.2 Multi-Channel and Single Channel Operation

The multi-channel package of the LDC enables the user to save board space and support flexible system design. For example, temperature drift can often cause a shift in component values, resulting in a shift in resonant frequency of the sensor. Using a 2nd sensor as a reference provides the capability to cancel out a temperature shift. When operated in multi-channel mode, the LDC sequentially samples the active channels. In single channel mode, the LDC samples a single channel, which is selectable. Table 3 shows the registers and values that are used to configure either multi-channel or single channel modes.

Table 3. Single and Multi-Channel Configuration Registers

MODE REGISTER FIELD [ BIT(S) ] VALUE(1)
Single channel CONFIG, addr 0x1A ACTIVE_CHAN [15:14] 00 = chan 0
01 = chan 1
10 = chan 2
11 = chan 3
MUX_CONFIG addr 0x1B AUTOSCAN_EN [15] 0 = continuous conversion on a single channel (default)
Multi-channel MUX_CONFIG addr 0x1B AUTOSCAN_EN [15] 1 = continuous conversion on multiple channels
MUX_CONFIG addr 0x1B RR_SEQUENCE [14:13] 00 = Ch0, Ch 1
01 = Ch0, Ch 1, Ch 2
10 = Ch0, CH1, Ch2, Ch3
(1) Channels 2 and 3 are only available for LDC1314

The digitized sensor measurement for each channel (DATAx) represents the ratio of the sensor frequency to the reference frequency. The data outputs represent the 12 MSBs of a 16-bit result:

Equation 1. DATAx/ 212 = fSENSORx/fREFx

The sensor frequency can be calculated from:

Equation 2. LDC1312-Q1 LDC1314-Q1 eq16_snoscy9.gif

Table 4 shows the registers that contain the fixed point sample values for each channel.

Table 4. LDC1314/1312 Sample Data Registers

CHANNEL(1) REGISTER FIELD NAME [BITS(S) ] VALUE
0 DATA_MSB_CH0, addr 0x00 DATA0 [11:0] 12 bits of the 16 bit result.
0x000 = under range
0xfff = over range
1 DATA_MSB_CH1, addr 0x02 DATA1 [11:0] 12 bits of the 16 bit result.
0x000 = under range
0xfff = over range
2 DATA_MSB_CH2, addr 0x04 DATA2 [11:0] 12 bits of the 16 bit result.
0x000 = under range
0xfff = over range
3 DATA_MSB_CH3, addr 0x06 DATA3 [11:0] 12 bits of the 16 bit result.
0x000 = under range
0xfff = over range
(1) Channels 2 and 3 available for LDC1314 only.

When the LDC sequences through the channels in multi-channel mode, the dwell time interval for each channel is the sum of 3 parts: sensor activation time + conversion time + channel switch delay.

The sensor activation time is the amount of settling time required for the sensor oscillation to stabilize, as shown in Figure 12. The settling wait time is programmable and should be set to a value that is long enough to allow stable oscillation. The settling wait time for channel x is given by:

Equation 3. tSx = (CHX_SETTLECOUNTË£16)/fREFx

Table 5 shows the registers and values for configuring the settling time for each channel.

LDC1312-Q1 LDC1314-Q1 sequential_mode_ch_seq_snoscy9.gif Figure 12. Multi-channel Mode Sequencing
LDC1312-Q1 LDC1314-Q1 single_ch_conv_mode_snoscy9.gif Figure 13. Single-channel Mode Sequencing

Table 5. Settling Time Register Configuration

CHANNEL(1) REGISTER FIELD CONVERSION TIME(2)
0 SETTLECOUNT_CH0, addr 0x10 CH0_SETTLECOUNT (15:0) (CH0_SETTLECOUNT*16)/fREF0
1 SETTLECOUNT_CH1, addr 0x11 CH1_SETTLECOUNT (15:0) (CH1_SETTLECOUNT*16)/fREF1
2 SETTLECOUNT_CH2, addr 0x12 CH2_SETTLECOUNT (15:0) (CH2_SETTLECOUNT*16)/fREF2
3 SETTLECOUNT_CH3, addr 0x13 CH3_SETTLECOUNT (15:0) (CH3_SETTLECOUNT*16)/fREF3
(1) Channels 2 and 3 are available only in the LDC1314.
(2) fREFx is the reference frequency configured for the channel.

The SETTLECOUNT for any channel x must satisfy:

Equation 4. CHx_SETTLECOUNT ≥ QSENSORx × fREFx / (16 × fSENSORx)

where

  • fSENSORx = Frequency of the Sensor on Channel x
  • fREFx = Reference frequency for Channel x
  • QSENSORx = Quality factor of the sensor on Channel x, where Q can be calculated by:
Equation 5. LDC1312-Q1 LDC1314-Q1 eq02_snoscy9.gif

Round the result to the next highest integer (for example, if Equation 4 recommends a minimum value of 6.08, program the register to 7 or higher).

L, RP and C values can be obtained by using Texas Instrument’s WEBENCH® for the coil design.

The conversion time represents the number of reference clock cycles used to measure the sensor frequency. It is set by the CHx_RCOUNT register for the channel. The conversion time for any channel x is:

Equation 6. tCx = (CHx_RCOUNT ˣ 16 + 4) /fREFx

The reference count value must be chosen to support the required number of effective bits (ENOB). For details, refer to the application note Optimizing L Measurement Resolution for the LDC161x and LDC1101.

Table 6. Conversion Time Configuration Registers, Channels 0 - 3(1)

CHANNEL REGISTER FIELD [ BIT(S) ] CONVERSION TIME
0 RCOUNT_CH0, addr 0x08 CH0_RCOUNT (15:0) (CH0_RCOUNT*16)/fREF0
1 RCOUNT_CH1, addr 0x09 CH1_RCOUNT (15:0) (CH1_RCOUNT*16)/fREF1
2 RCOUNT_CH2, addr 0x0A CH2_RCOUNT (15:0) (CH2_RCOUNT*16)/fREF2
3 RCOUNT_CH3, addr 0x0B CH3_RCOUNT (15:0) (CH3_RCOUNT*16)/fREF3
(1) Channels 2 and 3 are available only for LDC1314.

The typical channel switch delay time between the end of conversion and the beginning of sensor activation of the subsequent channel is:

Equation 7. Channel Switch Delay = 692 ns + 5 / fref

The deterministic conversion time of the LDC allows data polling at a fixed interval. A data ready flag (DRDY) is also available for interrupt driven system designs (see the STATUS register description in Register Maps).

An offset value may be subtracted from each DATA value to compensate for a frequency offset or maximize the dynamic range of the sample data. The offset values should be < fSENSORx_MIN / fREFx. Otherwise, the offset might be so large that it masks the LSBs which are changing.

Table 7. Frequency Offset Registers

CHANNEL(1) REGISTER FIELD [ BIT(S) ] VALUE
0 OFFSET_CH0, addr 0x0C CH0_OFFSET [ 15:0 ] fOFFSET0 = CH0_OFFSET * (fREF0/216)
1 OFFSET_CH1, addr 0x0D CH1_OFFSET [ 15:0 ] fOFFSET1 = CH1_OFFSET * (fREF1/216)
2 OFFSET_CH2, addr 0x0E CH2_OFFSET [ 15:0 ] fOFFSET2 = CH2_OFFSET * (fREF2/216)
3 OFFSET_CH3, addr 0x0F CH3_OFFSET [ 15:0 ] fOFFSET3 = CH3_OFFSET * (fREF3/216)
(1) Channels 2 and 3 are only available for LDC1314

Internally, the LDC measures with 16bits of resolution, while the conversion output word width is only 12bits. For systems in which the sensor signal variation is less than 25% of the full scale range, the LDC can report conversion results with higher resolution by setting the output gain. The output gain is applied to all device channels. An output gain can be used to apply a 2-bit, 3-bit, or 4-bit shift to the output code for all channels, allowing access to the 4LSBs of the original 16-bit result. The MSBs of the sample are shifted out when a gain is applied. Do not use the output gain if the MSBs of any active channel are toggling, as the MSBs for that channel will be lost when gain is applied.

Table 8. Output Gain Register

CHANNEL(1) REGISTER FIELD [ BIT(S) ] VALUES EFFECTIVE RESOLUTION (BITS) OUTPUT RANGE
All RESET_DEV, addr 0x1C OUTPUT_GAIN [ 10:9 ] 00 (default): Gain =1 (0 bits shift) 12 100% full scale
01: Gain = 4 (2 bits left shift) 14 25% full scale
10: Gain = 8 (3 bits left shift) 15 12.5% full scale
11 : Gain = 16 (4 bits left shift) 16 6.25% full scale
(1) Channels 2 and 3 are available for LDC1314 only.

Example: If the conversion result for a channel is 0x07A3, with OUTPUT_GAIN=0x0, the reported output code is 0x07A. If OUTPUT_GAIN is set to 0x3 in the same condition, then the reported output code is 0x7A3. The original 4 MSBs (0x0) are no longer accessible. Figure 14 shows the segments of the 16-bit sample that is reported for each possible gain setting.

LDC1312-Q1 LDC1314-Q1 conversion_data_output_gain_snoscy9.gif Figure 14. Conversion Data Output Gain

The sensor frequency can be determined by:

Equation 8. LDC1312-Q1 LDC1314-Q1 eq21_snoscy9.gif

where

  • DATAx = Conversion result from the DATA_CHx register
  • CHx_OFFSET = Offset value set in the OFFSET_CHx register
  • OUTPUT_GAIN = output multiplication factor set in the RESET_DEVICE.OUTPUT_GAIN register

8.3.3 Current Drive Control Registers

The registers listed in Table 9 are used to control the sensor drive current. The recommendations listed in the last column of Table 9 should be followed.

Auto-calibration mode is used to determine the optimal sensor drive current for a fixed sensor design. This mode should only be used during system prototyping.

The auto-amplitude correction attempts to maintain the sensor oscillation amplitude between 1.2V and 1.8V by adjusting the sensor drive current between conversions. When auto-amplitude correction is enabled, the output data may show non-monotonic behavior due to an adjustment in drive current. Auto-amplitude correction is only recommended for low-precision applications.

A high sensor current drive mode can be enabled to drive sensor coils with > 1.5mA on channel 0, only in single channel mode. This feature can be used when the sensor RP is lower than 1kΩ. Set the HIGH_CURRENT_DRV register bit to b1 to enable this mode.

Table 9. Current Drive Control Registers

CHANNEL(1) REGISTER FIELD [ BIT(S) ] VALUE
All CONFIG, addr 0x1A SENSOR_ACTIVATE_SEL [11] Sets current drive for sensor activation. Recommended value is b0 (Full Current mode).
RP_OVERRIDE_EN [12] Set to b1 for normal operation (RP over ride enabled)
AUTO_AMP_DIS [10] Disables Automatic amplitude correction. Set to b1 for normal operation (disabled)
0 CONFIG, addr 0x1A HIGH_CURRENT_DRV [6] b0 = normal current drive (1.5 mA)
b1 = Increased current drive (> 1.5 mA) for Ch 0 in single channel mode only. Cannot be used in multi-channel mode.
0 DRIVE_CURRENT_CH0, addr 0x1E CH0_IDRIVE [15:11] Drive current used during the settling and conversion time for Ch. 0 (auto-amplitude correction must be disabled and RP over ride=1 )
CH0_INIT_IDRIVE [10:6] Initial drive current stored during auto-calibration. Not used for normal operation.
1 DRIVE_CURRENT_CH1, addr 0x1F CH1_IDRIVE [15:11] Drive current used during the settling and conversion time for Ch. 1 (auto-amplitude correction must be disabled and RP over ride=1 )
CH1_INIT_IDRIVE [10:6] Initial drive current stored during auto-calibration. Not used for normal operation.
2 DRIVE_CURRENT_CH2, addr 0x20 CH2_IDRIVE [15:11] Drive current used during the settling and conversion time for Ch. 2 (auto-amplitude correction must be disabled and RP over ride=1 )
CH2_INIT_IDRIVE [10:6] Initial drive current stored during auto-calibration. Not used for normal operation.
3 DRIVE_CURRENT_CH3, addr 0x21 CH3_IDRIVE [15:11] Drive current used during the settling and conversion time for Ch. 3 (auto-amplitude correction must be disabled and RP over ride=1 )
CH3_INIT_IDRIVE [10:6] Initial drive current stored during auto-calibration. Not used for normal operation.
(1) Channels 2 and 3 are available for LDC1314 only.

If the RP value of the sensor attached to channel x is known, Table 10 can be used to select the 5-bit value to be programmed into the CHx_IDRIVE field for the channel. If the measured RP (at maximum spacing between the sensor and the target) falls between two of the table values, use the current drive value associated with the lower RP from Table 10. All channels that use an identical sensor/target configuration should use the same IDRIVE value.

Table 10. CHx_IDRIVE Values for Maximum Measured RP.

MEASURED RP (kΩ) CHx_IDRIVE REGISTER FIELD VALUE, BINARY (BITS [15:11] ) NOMINAL CURRENT (μA)
90.0 b00000 16
77.6 b00001 18
66.9 b00010 20
57.6 b00011 23
49.7 b00100 28
42.8 b00101 32
36.9 b00110 40
31.8 b00111 46
27.4 b01000 52
23.3 b01001 59
20.4 b01010 72
17.6 b01011 82
15.1 b01100 95
13.0 b01101 110
11.2 b01110 127
9.7 b01111 146
8.4 b10000 169
7.2 b10001 195
6.2 b10010 212
5.4 b10011 244
4.6 b10100 297
4.0 b10101 342
3.4 b10110 424
3.0 b10111 489
2.5 b11000 551
2.2 b11001 635
1.9 b11010 763
1.6 b11011 880
1.4 b11100 1017
1.2 b11101 1173
1.0 b11110 1355
0.9 b11111 1563

If the RP is not known, the following steps for auto-calibration can be used to configure the needed drive current, either during system prototyping, or during normal startup if feasible:

  1. Set target at the maximum planned operating distance from the sensor.
  2. Place the device into SLEEP mode by setting CONFIG.SLEEP_MODE_EN to b0.
  3. Program the desired values of SETTLECOUNT and RCOUNT values for the channel.
  4. Enable auto-calibration by setting RP_OVERDRIVE_EN to b0.
  5. Take the device out of SLEEP mode by setting CONFIG.SLEEP_MODE_EN to b1.
  6. Allow the device to perform at least one measurement, with the target stable (fixed) at the maximum operating range.
  7. Read the channel current drive value from the appropriate DRIVE_CURRENT_CHx register (addresses 0x1e, 0x1f, 0x20, or 0x21), in the CHx_INIT_DRIVE field (bits 10:6). Save this value.
  8. During startup for normal operating mode, write the value saved from the CHx_INIT_DRIVE bit field into the Chx_IDRIVE bit field (bits 15:11).
  9. During normal operating mode, the RP_OVERRIDE_EN must set to b1 to force the fixed current drive.

If the current drive results in the oscillation amplitude greater than 1.8V, the internal ESD clamping circuit will become active. This may cause the sensor frequency to shift so that the output values no longer represent a valid system state. If the current drive is set at a lower value, the SNR performance of the system will decrease, and at near zero target range, oscillations may completely stop, and the output sample values will be all zeroes.

8.3.4 Device Status Registers

The registers listed in Table 11 may be used to read device status.

Table 11. Status Registers

CHANNEL(1) REGISTER FIELDS [ BIT(S) ] VALUES
All STATUS, addr 0x18 12 fields are available that contain various status bits [ 15:0 ] Refer to Register Maps section for a description of the individual status bits.
All ERROR_CONFIG, addr 0x19 12 fields are available that are used to configure error reporting [ 15:0 ] Refer to Register Maps section for a description of the individual error configuration bits.
(1) Channels 2 and 3 are available for LDC1314 only.

See the STATUS and ERROR_CONFIG register description in the Register Map section. These registers can be configured to trigger an interrupt on the INTB pin for certain events. The following conditions must be met:

  1. The error or status register must be unmasked by enabling the appropriate register bit in the ERROR_CONFIG register
  2. The INTB function must be enabled by setting CONFIG.INTB_DIS to 0

When a bit field in the STATUS register is set, the entire STATUS register content is held until read or until the DATA_CHx register is read. Reading also de-asserts INTB.

Interrupts are cleared by one of the following events:

  1. Entering Sleep Mode
  2. Power-on reset (POR)
  3. Device enters Shutdown Mode (SD is asserted)
  4. S/W reset
  5. I2C read of the STATUS register: Reading the STATUS register will clear any error status bit set in STATUS along with the ERR_CHAN field and de-assert INTB

Setting register CONFIG.INTB_DIS to b1 disables the INTB function and holds the INTB pin high.

8.3.5 Input Deglitch Filter

The input deglitch filter suppresses EMI and ringing above the sensor frequency. It does not impact the conversion result as long as its bandwidth is configured to be above the maximum sensor frequency. The input deglitch filter can be configured in MUX_CONFIG.DEGLITCH register field as shown in Table 12. For optimal performance, TI recommends to select the lowest setting that exceeds the sensor oscillation frequency. For example, if the maximum sensor frequency is 2.0 MHz, choose MUX_CONFIG.DEGLITCH = b100 (3.3 MHz).

Table 12. Input deglitch filter register

CHANNEL(1) MUX_CONFIG.DEGLITCH REGISTER VALUE DEGLITCH FREQEUNCY
ALL 001 1 MHz
ALL 100 3.3 MHz
ALL 101 10 MHz
ALL 011 33 MHz
(1) Channels 2 and 3 are available for LDC1314 only.

8.4 Device Functional Modes

8.4.1 Startup Mode

When the LDC powers up, it enters into Sleep Mode and will wait for configuration. Once the device is configured, exit Sleep Mode by setting CONFIG.SLEEP_MODE_EN to b0.

TI recommends to configure the LDC while in Sleep Mode. If a setting on the LDC needs to be changed, return the device to Sleep Mode, change the appropriate register, and then exit Sleep Mode.

8.4.2 Normal (Conversion) Mode

When operating in the normal (conversion) mode, the LDC is periodically sampling the frequency of the sensor(s) and generating sample outputs for the active channel(s).

8.4.3 Sleep Mode

Sleep Mode is entered by setting the CONFIG.SLEEP_MODE_EN register field to 1. While in this mode, the device configuration is maintained. To exit Sleep Mode, set the CONFIG.SLEEP_MODE_EN register field to 0. After setting CONFIG.SLEEP_MODE_EN to b0, sensor activation for the first conversion will begin after 16,384 fINT clock cycles. While in Sleep Mode the I2C interface is functional so that register reads and writes can be performed. While in Sleep Mode, no conversions are performed. In addition, entering Sleep Mode will clear conversion results, any error condition and de-assert the INTB pin.

8.4.4 Shutdown Mode

When the SD pin is set to high, the LDC will enter Shutdown Mode. Shutdown Mode is the lowest power state. To exit Shutdown Mode, set the SD pin to low. Entering Shutdown Mode will return all registers to their default state.

While in Shutdown Mode, no conversions are performed. In addition, entering Shutdown Mode will clear any error condition and de-assert the INTB pin. While the device is in Shutdown Mode, is not possible to read to or write from the device via the I2C interface.

8.4.4.1 Reset

The LDC can be reset by writing to RESET_DEV.RESET_DEV. Any active conversion will stop and all register values will return to their default value. This register bit will always return 0b when read.

8.5 Programming

The LDC device uses an I2C interface to access control and data registers.

8.5.1 I2C Interface Specifications

The LDC uses an extended start sequence with I2C for register access. The maximum speed of the I2C interface is 400kbit/s. This sequence follows the standard I2C 7bit slave address followed by an 8bit pointer register byte to set the register address. When the ADDR pin is set low, the LDC I2C address is 0x2A; when the ADDR pin is set high, the LDC I2C address is 0x2B. The ADDR pin must not change state after the LDC exits Shutdown Mode.

LDC1312-Q1 LDC1314-Q1 td_I2C_write_reg_seq_snoscy9.gif Figure 15. I2C Write Register Sequence
LDC1312-Q1 LDC1314-Q1 td_I2C_read_reg_seq_snoscy9.gif Figure 16. I2C Read Register Sequence

8.6 Register Maps

8.6.1 Register List

Fields indicated with Reserved must be written only with indicated values, otherwise improper device operation may occur. The R/W column indicates the Read-Write status of the corresponding field. A ‘R/W’ entry indicates read and write capability, a ‘R’ indicates read-only, and a ‘W’ indicates write-only.

Figure 17. Register List
ADDRESS NAME DEFAULT VALUE DESCRIPTION
0x00 DATA_CH0 0x0000 Channel 0 Conversion Result and Error Status
0x02 DATA_CH1 0x0000 Channel 1 Conversion Result and Error Status
0x04 DATA_CH2 0x0000 Channel 2 Conversion Result and Error Status (LDC1314 only)
0x06 DATA_CH3 0x0000 Channel 3 Conversion Result and Error Status (LDC1314 only)
0x08 RCOUNT_CH0 0x0080 Reference Count setting for Channel 0
0x09 RCOUNT_CH1 0x0080 Reference Count setting for Channel 1
0x0A RCOUNT_CH2 0x0080 Reference Count setting for Channel 2. (LDC1314 only)
0x0B RCOUNT_CH3 0x0080 Reference Count setting for Channel 3.(LDC1314 only)
0x0C OFFSET_CH0 0x0000 Offset value for Channel 0
0x0D OFFSET_CH1 0x0000 Offset value for Channel 1
0x0E OFFSET_CH2 0x0000 Offset value for Channel 2 (LDC1314 only)
0x0F OFFSET_CH3 0x0000 Offset value for Channel 3 (LDC1314 only)
0x10 SETTLECOUNT_CH0 0x0000 Channel 0 Settling Reference Count
0x11 SETTLECOUNT_CH1 0x0000 Channel 1 Settling Reference Count
0x12 SETTLECOUNT_CH2 0x0000 Channel 2 Settling Reference Count (LDC1314 only)
0x13 SETTLECOUNT_CH3 0x0000 Channel 3 Settling Reference Count (LDC1314 only)
0x14 CLOCK_DIVIDERS_CH0 0x0000 Reference and Sensor Divider settings for Channel 0
0x15 CLOCK_DIVIDERS_CH1 0x0000 Reference and Sensor Divider settings for Channel 1
0x16 CLOCK_DIVIDERS_CH2 0x0000 Reference and Sensor Divider settings for Channel 2 (LDC1314 only)
0x17 CLOCK_DIVIDERS_CH3 0x0000 Reference and Sensor Divider settings for Channel 3 (LDC1314 only)
0x18 STATUS 0x0000 Device Status Report
0x19 ERROR_CONFIG 0x0000 Error Reporting Configuration
0x1A CONFIG 0x2801 Conversion Configuration
0x1B MUX_CONFIG 0x020F Channel Multiplexing Configuration
0x1C RESET_DEV 0x0000 Reset Device
0x1E DRIVE_CURRENT_CH0 0x0000 Channel 0 sensor current drive configuration
0x1F DRIVE_CURRENT_CH1 0x0000 Channel 1 sensor current drive configuration
0x20 DRIVE_CURRENT_CH2 0x0000 Channel 2 sensor current drive configuration (LDC1314 only)
0x21 DRIVE_CURRENT_CH3 0x0000 Channel 3 sensor current drive configuration (LDC1314 only)
0x7E MANUFACTURER_ID 0x5449 Manufacturer ID
0x7F DEVICE_ID 0x3054 Device ID

8.6.2 Address 0x00, DATA_CH0

Figure 18. Address 0x00, DATA_CH0
15 14 13 12 11 10 9 8
CH0_ERR_UR CH0_ERR_OR CH0_ERR_WD CH0_ERR_AE DATA0[11:0]
7 6 5 4 3 2 1 0
DATA0[11:0]
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 13. Address 0x00, DATA_CH0 Field Descriptions

Bit Field Type Reset Description
15 CH0_ERR_UR R 0 Channel 0 Conversion Under-range Error Flag. Cleared by reading the bit.
14 CH0_ERR_OR R 0 Channel 0 Conversion Over-range Error Flag. Cleared by reading the bit.
13 CH0_ERR_WD R 0 Channel 0 Conversion Watchdog Timeout Error Flag. Cleared by reading the bit.
12 CH0_ERR_AE R 0 Channel 0 Conversion Watchdog Timeout Error Flag. Cleared by reading the bit.
11:0 DATA0[11:0] R 0000 0000 0000 Channel 0 Conversion Result

8.6.3 Address 0x02, DATA_CH1

Figure 19. Address 0x02, DATA_CH1
15 14 13 12 11 10 9 8
CH1_ERR_UR CH1_ERR_OR CH1_ERR_WD CH1_ERR_AE DATA1[11:0]
7 6 5 4 3 2 1 0
DATA1[11:0]
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 14. Address 0x02, DATA_CH1 Field Descriptions

Bit Field Type Reset Description
15 CH1_ERR_UR R 0 Channel 1 Conversion Under-range Error Flag. Cleared by reading the bit.
14 CH1_ERR_OR R 0 Channel 1 Conversion Over-range Error Flag. Cleared by reading the bit.
13 CH1_ERR_WD R 0 Channel 1 Conversion Watchdog Timeout Error Flag. Cleared by reading the bit.
12 CH1_ERR_AE R 0 Channel 1 Conversion Watchdog Timeout Error Flag. Cleared by reading the bit.
11:0 DATA1[11:0] R 0000 0000 0000 Channel 1 Conversion Result

8.6.4 Address 0x04, DATA_CH2 (LDC1314 only)

Figure 20. Address 0x04, DATA_CH2
15 14 13 12 11 10 9 8
CH2_ERR_UR CH2_ERR_OR CH2_ERR_WD CH2_ERR_AE DATA2[11:0]
7 6 5 4 3 2 1 0
DATA2[11:0]
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 15. Address 0x04, DATA_CH2 Field Descriptions

Bit Field Type Reset Description
15 CH2_ERR_UR R 0 Channel 2 Conversion Under-range Error Flag. Cleared by reading the bit.
14 CH2_ERR_OR R 0 Channel 2 Conversion Over-range Error Flag. Cleared by reading the bit.
13 CH2_ERR_WD R 0 Channel 2 Conversion Watchdog Timeout Error Flag. Cleared by reading the bit.
12 CH2_ERR_AE R 0 Channel 2 Conversion Watchdog Timeout Error Flag. Cleared by reading the bit.
11:0 DATA2[11:0] R 0000 0000 0000 Channel 2 Conversion Result

8.6.5 Address 0x06, DATA_CH3 (LDC1314 only)

Figure 21. Address 0x06, DATA_CH3
15 14 13 12 11 10 9 8
CH3_ERR_UR CH3_ERR_OR CH3_ERR_WD CH3_ERR_AE DATA3[11:0]
7 6 5 4 3 2 1 0
DATA3[11:0]
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16. Address 0x06, DATA_CH3 Field Descriptions

Bit Field Type Reset Description
15 CH3_ERR_UR R 0 Channel 3 Conversion Under-range Error Flag. Cleared by reading the bit.
14 CH3_ERR_OR R 0 Channel 3 Conversion Over-range Error Flag. Cleared by reading the bit.
13 CH3_ERR_WD R 0 Channel 3 Conversion Watchdog Timeout Error Flag. Cleared by reading the bit.
12 CH3_ERR_AE R 0 Channel 3 Conversion Watchdog Timeout Error Flag. Cleared by reading the bit.
11:0 DATA3[11:0] R 0000 0000 0000 Channel 3 Conversion Result

8.6.6 Address 0x08, RCOUNT_CH0

Figure 22. Address 0x08, RCOUNT_CH0
15 14 13 12 11 10 9 8
CH0_RCOUNT
7 6 5 4 3 2 1 0
CH0_RCOUNT
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17. Address 0x08, RCOUNT_CH0 Field Descriptions

Bit Field Type Reset Description
15:0 CH0_RCOUNT R/W 0000 0000 1000 0000 Channel 0 Reference Count Conversion Interval Time
0x0000-0x0004: Reserved
0x0005-0xFFFF: Conversion Time (tC0) = (CH0_RCOUNTË£16)/fREF0

8.6.7 Address 0x09, RCOUNT_CH1

Figure 23. Address 0x09, RCOUNT_CH1
15 14 13 12 11 10 9 8
CH1_RCOUNT
7 6 5 4 3 2 1 0
CH1_RCOUNT
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 18. Address 0x09, RCOUNT_CH1 Field Descriptions

Bit Field Type Reset Description
15:0 CH1_RCOUNT R/W 0000 0000 1000 0000 Channel 1 Reference Count Conversion Interval Time
0x0000-0x0004: Reserved
0x0005-0xFFFF: Conversion Time (tC1)= (CH1_RCOUNTË£16)/fREF1

8.6.8 Address 0x0A, RCOUNT_CH2 (LDC1314 only)

Figure 24. Address 0x0A, RCOUNT_CH2
15 14 13 12 11 10 9 8
CH2_RCOUNT
7 6 5 4 3 2 1 0
CH2_RCOUNT
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19. Address 0x0A, RCOUNT_CH2 Field Descriptions

Bit Field Type Reset Description
15:0 CH2_RCOUNT R/W 0000 0000 1000 0000 Channel 2 Reference Count Conversion Interval Time
0x0000-0x0004: Reserved
0x0005-0xFFFF: Conversion Time (tC2)= (CH2_RCOUNTË£16)/fREF2

8.6.9 Address 0x0B, RCOUNT_CH3 (LDC1314 only)

Figure 25. Address 0x0B, RCOUNT_CH3
15 14 13 12 11 10 9 8
CH3_RCOUNT
7 6 5 4 3 2 1 0
CH3_RCOUNT
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 20. Address 0x0B, RCOUNT_CH3 Field Descriptions

Bit Field Type Reset Description
15:0 CH3_RCOUNT R/W 0000 0000 1000 0000 Channel 3 Reference Count Conversion Interval Time
0x0000-0x0004: Reserved
0x0005-0xFFFF: Conversion Time (tC3)= (CH3_RCOUNTË£16)/fREF3

8.6.10 Address 0x0C, OFFSET_CH0

Figure 26. Address 0x0C, CH0_OFFSET
15 14 13 12 11 10 9 8
CH0_OFFSET
7 6 5 4 3 2 1 0
CH0_OFFSET
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21. CH0_OFFSET Field Descriptions

Bit Field Type Reset Description
15:0 CH0_OFFSET R/W 0000 0000 0000 0000 Channel 0 Conversion Offset. fOFFSET_0 = (CH0_OFFSET/216)*fREF0

8.6.11 Address 0x0D, OFFSET_CH1

Figure 27. Address 0x0D, OFFSET_CH1
15 14 13 12 11 10 9 8
CH1_OFFSET
7 6 5 4 3 2 1 0
CH1_OFFSET
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22. Address 0x0D, OFFSET_CH1 Field Descriptions

Bit Field Type Reset Description
15:0 CH1_OFFSET R/W 0000 0000 0000 0000 Channel 1 Conversion Offset. fOFFSET_1 = (CH1_OFFSET/216)*fREF1

8.6.12 Address 0x0E, OFFSET_CH2 (LDC1314 only)

Figure 28. Address 0x0E, OFFSET_CH2
15 14 13 12 11 10 9 8
CH2_OFFSET
7 6 5 4 3 2 1 0
CH2_OFFSET
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23. Address 0x0E, OFFSET_CH2 Field Descriptions

Bit Field Type Reset Description
15:0 CH2_OFFSET R/W 0000 0000 0000 0000 Channel 2 Conversion Offset. fOFFSET_2 = (CH2_OFFSET/216)*fREF2

8.6.13 Address 0x0F, OFFSET_CH3 (LDC1314 only)

Figure 29. Address 0x0F, OFFSET_CH3
15 14 13 12 11 10 9 8
CH3_OFFSET
7 6 5 4 3 2 1 0
CH3_OFFSET
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 24. Address 0x0F, OFFSET_CH3 Field Descriptions

Bit Field Type Reset Description
15:0 CH3_OFFSET R/W 0000 0000 0000 0000 Channel 3 Conversion Offset. fOFFSET_3 = (CH3_OFFSET/216)*fREF3

8.6.14 Address 0x10, SETTLECOUNT_CH0

Figure 30. Address 0x10, SETTLECOUNT_CH0
15 14 13 12 11 10 9 8
CH0_SETTLECOUNT
7 6 5 4 3 2 1 0
CH0_SETTLECOUNT
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 25. Address 0x11, SETTLECOUNT_CH0 Field Descriptions

Bit Field Type Reset Description
15:0 CH0_SETTLECOUNT R/W 0000 0000 0000 0000 Channel 0 Conversion Settling
The LDC will use this settling time to allow the LC sensor to stabilize before initiation of a conversion on Channel 0.
If the amplitude has not settled prior to the conversion start, an Amplitude error will be generated if reporting of this type of error is enabled.
0x0000: Settle Time (tS0)= 32 ÷ fREF0
0x0001: Settle Time (tS0)= 32 ÷ fREF0
0x0002- 0xFFFF: Settle Time (tS0)= (CH0_SETTLECOUNTË£16) ÷ fREF0

8.6.15 Address 0x11, SETTLECOUNT_CH1

Figure 31. Address 0x11, SETTLECOUNT_CH1
15 14 13 12 11 10 9 8
CH1_SETTLECOUNT
7 6 5 4 3 2 1 0
CH1_SETTLECOUNT
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 26. Address 0x12, SETTLECOUNT_CH1 Field Descriptions

Bit Field Type Reset Description
15:0 CH1_SETTLECOUNT R/W 0000 0000 0000 0000 Channel 1 Conversion Settling
The LDC will use this settling time to allow the LC sensor to stabilize before initiation of a conversion on a Channel 1.
If the amplitude has not settled prior to the conversion start, an Amplitude error will be generated if reporting of this type of error is enabled.
0x0000: Settle Time (tS1)= 32 ÷ fREF1
0x0001: Settle Time (tS1)= 32 ÷ fREF1
0x0002- 0xFFFF: Settle Time (tS1)= (CH1_SETTLECOUNTË£16) ÷ fREF1

8.6.16 Address 0x12, SETTLECOUNT_CH2 (LDC1314 only)

Figure 32. Address 0x12, SETTLECOUNT_CH2
15 14 13 12 11 10 9 8
CH2_SETTLECOUNT
7 6 5 4 3 2 1 0
CH2_SETTLECOUNT
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 27. Address 0x12, SETTLECOUNT_CH2 Field Descriptions

Bit Field Type Reset Description
15:0 CH2_SETTLECOUNT R/W 0000 0000 0000 0000 Channel 2 Conversion Settling
The LDC will use this settling time to allow the LC sensor to stabilize before initiation of a conversion on Channel 2.
If the amplitude has not settled prior to the conversion start, an Amplitude error will be generated if reporting of this type of error is enabled.
0x0000: Settle Time (tS2)= 32 ÷ fREF2
0x0001: Settle Time (tS2)= 32 ÷ fREF2
0x0002- 0xFFFF: Settle Time (tS2)= (CH2_SETTLECOUNTË£16) ÷ fREF2

8.6.17 Address 0x13, SETTLECOUNT_CH3 (LDC1314 only)

Figure 33. Address 0x13, SETTLECOUNT_CH3
15 14 13 12 11 10 9 8
CH3_SETTLECOUNT
7 6 5 4 3 2 1 0
CH3_SETTLECOUNT
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 28. Address 0x13, SETTLECOUNT_CH3 Field Descriptions

Bit Field Type Reset Description
15:0 CH3_SETTLECOUNT R/W 0000 0000 0000 0000 Channel 3 Conversion Settling
The LDC will use this settling time to allow the LC sensor to stabilize before initiation of a conversion on Channel 3.
If the amplitude has not settled prior to the conversion start, an Amplitude error will be generated if reporting of this type of error is enabled
0x0000: Settle Time (tS3)= 32 ÷ fREF3
0x0001: Settle Time (tS3)= 32 ÷ fREF3
0x0002- 0xFFFF: Settle Time (tS3)= (CH3_SETTLECOUNTË£16) ÷ fREF3

8.6.18 Address 0x14, CLOCK_DIVIDERS_CH0

Figure 34. Address 0x14, CLOCK_DIVIDERS_CH0
15 14 13 12 11 10 9 8
CH0_FIN_DIVIDER RESERVED CH0_FREF_DIVIDER
7 6 5 4 3 2 1 0
CH0_FREF_DIVIDER
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 29. Address 0x14, CLOCK_DIVIDERS_CH0 Field Descriptions

Bit Field Type Reset Description
15:12 CH0_FIN_DIVIDER R/W 0000 Channel 0 Input Divider Sets the divider for Channel 0 input. Must be set to ≥2 if the Sensor frequency is ≥ 8.75MHz
b0000: Reserved. Do not use.
CH0_FIN_DIVIDER≥b0001:
fin0 = fSENSOR0/CH0_FIN_DIVIDER
11:10 RESERVED R/W 00 Reserved. Set to b00.
9:0 CH0_FREF_DIVIDER R/W 00 0000 0000 Channel 0 Reference Divider Sets the divider for Channel 0 reference. Use this to scale the maximum conversion frequency.
b00’0000’0000: Reserved. Do not use.
CH0_FREF_DIVIDER≥b00’0000’0001:
fREF0 = fCLK/CH0_FREF_DIVIDER

8.6.19 Address 0x15, CLOCK_DIVIDERS_CH1

Figure 35. Address 0x15, CLOCK_DIVIDERS_CH1
15 14 13 12 11 10 9 8
CH1_FIN_DIVIDER RESERVED CH1_FREF_DIVIDER
7 6 5 4 3 2 1 0
CH1_FREF_DIVIDER
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 30. Address 0x15, CLOCK_DIVIDERS_CH1 Field Descriptions

Bit Field Type Reset Description
15:12 CH1_FIN_DIVIDER R/W 0000 Channel 1 Input Divider. Sets the divider for Channel 1 input. Used when the Sensor frequency is greater than the maximum FIN.
b0000: Reserved. Do not use.
CH1_FIN_DIVIDER≥b0001:
fin1 = fSENSOR1/CH1_FIN_DIVIDER
11:10 RESERVED R/W 00 Reserved. Set to b00.
9:0 CH1_FREF_DIVIDER R/W 00 0000 0000 Channel 1 Reference Divider. Sets the divider for Channel 1 reference. Use this to scale the maximum conversion frequency.
b00’0000’0000: Reserved. Do not use.
CH1_FREF_DIVIDER≥ b00’0000’0001:
fREF1 = fCLK/CH1_FREF_DIVIDER

8.6.20 Address 0x16, CLOCK_DIVIDERS_CH2 (LDC1314 only)

Figure 36. Address 0x16, CLOCK_DIVIDERS_CH2
15 14 13 12 11 10 9 8
CH2_FIN_DIVIDER RESERVED CH2_FREF_DIVIDER
7 6 5 4 3 2 1 0
CH2_FREF_DIVIDER
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 31. Address 0x16, CLOCK_DIVIDERS_CH2 Field Descriptions

Bit Field Type Reset Description
15:12 CH2_FIN_DIVIDER R/W 0000 Channel 2 Input Divider. Sets the divider for Channel 2 input. Must be set to ≥2 if the Sensor frequency is ≥ 8.75MHz.
b0000: Reserved. Do not use.
CH2_FIN_DIVIDER≥b0001:
fIN2 = fSENSOR2/CH2_FIN_DIVIDER
11:10 RESERVED R/W 00 Reserved. Set to b00
9:0 CH2_FREF_DIVIDER R/W 00 0000 0000 Channel 2 Reference Divider. Sets the divider for Channel 2 reference. Use this to scale the maximum conversion frequency.
b00’0000’0000: Reserved. Do not use.
CH2_FREF_DIVIDER ≥ b00’0000’0001: fREF2 = fCLK/CH2_FREF_DIVIDER

8.6.21 Address 0x17, CLOCK_DIVIDERS_CH3 (LDC1314 only)

Figure 37. Address 0x17, CLOCK_DIVIDERS_CH3
15 14 13 12 11 10 9 8
CH3_FIN_DIVIDER RESERVED CH3_FREF_DIVIDER
7 6 5 4 3 2 1 0
CH3_FREF_DIVIDER
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 32. Address 0x17, CLOCK_DIVIDERS_CH3

Bit Field Type Reset Description
15:12 CH3_FIN_DIVIDER R/W 0000 Channel 3 Input Divider. Sets the divider for Channel 3 input. Must be set to ≥2 if the Sensor frequency is ≥ 8.75MHz.
b0000: Reserved. Do not use.
CH3_FIN_DIVIDER≥b0001:
fIN3 = fSENSOR3/CH3_FIN_DIVIDER
11:10 RESERVED R/W 00 Reserved. Set to b00
9:0 CH3_FREF_DIVIDER R/W 00 0000 0000 Channel 3 Reference Divider. Sets the divider for Channel 3 reference. Use this to scale the maximum conversion frequency.
b00’0000’0000: reserved
CH3_FREF_DIVIDER ≥ b00’0000’0001: fREF3 = fCLK/CH3_FREF_DIVIDER

8.6.22 Address 0x18, STATUS

Figure 38. Address 0x18, STATUS
15 14 13 12 11 10 9 8
ERR_CHAN ERR_UR ERR_OR ERR_WD ERR_AHE ERR_ALE ERR_ZC
7 6 5 4 3 2 1 0
RESERVED DRDY RESERVED CH0_UNREADCONV CH1_ UNREADCONV CH2_ UNREADCONV CH3_ UNREADCONV
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 33. Address 0x18, STATUS Field Descriptions

Bit Field Type Reset Description
15:14 ERR_CHAN R 00 Error Channel
Indicates which channel has generated a Flag or Error. Once flagged, any reported error is latched and maintained until either the STATUS register or the DATA_CHx register corresponding to the Error Channel is read.
b00: Channel 0 is source of flag or error.
b01: Channel 1 is source of flag or error.
b10: Channel 2 is source of flag or error (LDC1314 only).
b11: Channel 3 is source of flag or error (LDC1314 only).
13 ERR_UR R 0 Conversion Under-range Error
b0: No Conversion Under-range error was recorded since the last read of the STATUS register.
b1: An active channel has generated a Conversion Under-range error. Refer to STATUS.ERR_CHAN field to determine which channel is the source of this error.
12 ERR_OR R 0 Conversion Over-range Error.
b0: No Conversion Over-range error was recorded since the last read of the STATUS register.
b1: An active channel has generated a Conversion Over-range error. Refer to STATUS.ERR_CHAN field to determine which channel is the source of this error.
11 ERR_WD R 0 Watchdog Timeout Error
b0: No Watchdog Timeout error was recorded since the last read of the STATUS register.
b1: An active channel has generated a Watchdog Timeout error. Refer to STATUS.ERR_CHAN field to determine which channel is the source of this error.
10 ERR_AHE R 0 Amplitude High Error
b0: No Amplitude High error was recorded since the last read of the STATUS register.
b1: An active channel has generated an Amplitude High error. Refer to STATUS.ERR_CHAN field to determine which channel is the source of this error.
9 ERR_ALE R 0 Amplitude Low Error
b0: No Amplitude Low error was recorded since the last read of the STATUS register.
b1: An active channel has generated an Amplitude Low error. Refer to STATUS.ERR_CHAN field to determine which channel is the source of this error.
8 ERR_ZC R 0 Zero Count Error
b0: No Zero Count error was recorded since the last read of the STATUS register.
b1: An active channel has generated a Zero Count error. Refer to STATUS.ERR_CHAN field to determine which channel is the source of this error.
6 DRDY R 0 Data Ready Flag.
b0: No new conversion result was recorded in the STATUS register.
b1: A new conversion result is ready. When in Single Channel Conversion, this indicates a single conversion is available. When in sequential mode, this indicates that a new conversion result for all active channels is now available.
3 CH0_UNREADCONV R 0 Channel 0 Unread Conversion b0: No unread conversion is present for Channel 0.
b1: An unread conversion is present for Channel 0.
Read Register DATA_CH0 to retrieve conversion results.
2 CH1_ UNREADCONV R 0 Channel 1 Unread Conversion b0: No unread conversion is present for Channel 1.
b1: An unread conversion is present for Channel 1.
Read Register DATA_CH1 to retrieve conversion results.
1 CH2_ UNREADCONV R 0 Channel 2 Unread Conversion b0: No unread conversion is present for Channel 2.
b1: An unread conversion is present for Channel 2.
Read Register DATA_CH2 to retrieve conversion results (LDC1314 only)
0 CH3_ UNREADCONV R 0 Channel 3 Unread Conversion
b0: No unread conversion is present for Channel 3.
b1: An unread conversion is present for Channel 3.
Read Register DATA_CH3 to retrieve conversion results (LDC1314 only)

8.6.23 Address 0x19, ERROR_CONFIG

Figure 39. Address 0x19, ERROR_CONFIG
15 14 13 12 11 10 9 8
UR_ERR2OUT OR_ERR2OUT WD_ ERR2OUT AH_ERR2OUT AL_ERR2OUT RESERVED
7 6 5 4 3 2 1 0
UR_ERR2INT OR_ERR2INT WD_ERR2INT AH_ERR2INT AL_ERR2INT ZC_ERR2INT Reserved DRDY_2INT
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 34. Address 0x19, ERROR_CONFIG

Bit Field Type Reset Description
15 UR_ERR2OUT R/W 0 Under-range Error to Output Register
b0: Do not report Under-range errors in the DATA_CHx registers.
b1: Report Under-range errors in the DATA_CHx.CHx_ERR_UR register field corresponding to the channel that generated the error.
14 OR_ERR2OUT R/W 0 Over-range Error to Output Register
b0: Do not report Over-range errors in the DATA_CHx registers.
b1: Report Over-range errors in the DATA_CHx.CHx_ERR_OR register field corresponding to the channel that generated the error.
13 WD_ ERR2OUT R/W 0 Watchdog Timeout Error to Output Register
b0: Do not report Watchdog Timeout errors in the DATA_CHx registers.
b1: Report Watchdog Timeout errors in the DATA_CHx.CHx_ERR_WD register field corresponding to the channel that generated the error.
12 AH_ERR2OUT R/W 0 Amplitude High Error to Output Register
b0:Do not report Amplitude High errors in the DATA_CHx registers.
b1: Report Amplitude High errors in the DATA_CHx.CHx_ERR_AE register field corresponding to the channel that generated the error.
11 AL_ERR2OUT R/W 0 Amplitude Low Error to Output Register
b0: Do not report Amplitude High errors in the DATA_CHx registers.
b1: Report Amplitude High errors in the DATA_CHx.CHx_ERR_AE register field corresponding to the channel that generated the error.
7 UR_ERR2INT R/W 0 Under-range Error to INTB
b0: Do not report Under-range errors by asserting INTB pin and STATUS register.
b1: Report Under-range errors by asserting INTB pin and updating STATUS.ERR_UR register field.
6 OR_ERR2INT R/W 0 Over-range Error to INTB
b0: Do not report Over-range errors by asserting INTB pin and STATUS register.
b1: Report Over-range errors by asserting INTB pin and updating STATUS.ERR_OR register field.
5 WD_ERR2INT R/W 0 Watchdog Timeout Error to INTB b0: Do not report Under-range errors by asserting INTB pin and STATUS register.
b1: Report Watchdog Timeout errors by asserting INTB pin and updating STATUS.ERR_WD register field.
4 AH_ERR2INT R/W 0 Amplitude High Error to INTB b0: Do not report Amplitude High errors by asserting INTB pin and STATUS register.
b1: Report Amplitude High errors by asserting INTB pin and updating STATUS.ERR_AHE register field.
3 AL_ERR2INT R/W 0 Amplitude Low Error to INTB b0: Do not report Amplitude Low errors by asserting INTB pin and STATUS register.
b1: Report Amplitude Low errors by asserting INTB pin and updating STATUS.ERR_ALE register field.
2 ZC_ERR2INT R/W 0 Zero Count Error to INTB b0: Do not report Zero Count errors by asserting INTB pin and STATUS register.
b1: Report Zero Count errors by asserting INTB pin and updating STATUS. ERR_ZC register field.
1 Reserved R/W 0 Reserved (set to b0)
0 DRDY_2INT R/W 0 Data Ready Flag to INTB b0: Do not report Data Ready Flag by asserting INTB pin and STATUS register.
b1: Report Data Ready Flag by asserting INTB pin and updating STATUS. DRDY register field.

8.6.24 Address 0x1A, CONFIG

Figure 40. Address 0x1A, CONFIG
15 14 13 12 11 10 9 8
ACTIVE_CHAN SLEEP_MODE_EN RP_OVERRIDE_EN SENSOR_ACTIVATE_SEL AUTO_AMP_DIS REF_CLK_SRC RESERVED
7 6 5 4 3 2 1 0
INTB_DIS HIGH_CURRENT_DRV RESERVED
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 35. Address 0x1A, CONFIG Field Descriptions

Bit Field Type Reset Description
15:14 ACTIVE_CHAN R/W 00 Active Channel Selection
Selects channel for continuous conversions when MUX_CONFIG.SEQUENTIAL is 0.
b00: Perform continuous conversions on Channel 0
b01: Perform continuous conversions on Channel 1
b10: Perform continuous conversions on Channel 2 (LDC1314 only)
b11: Perform continuous conversions on Channel 3 (LDC1314 only)
13 SLEEP_MODE_EN R/W 1 Sleep Mode Enable
Enter or exit low power Sleep Mode.
b0: Device is active.
b1: Device is in Sleep Mode.
12 RP_OVERRIDE_EN R/W 0 Sensor RP Override Enable
Provides control over Sensor current drive used during the conversion time for Ch. x, based on the programmed value in the CHx_IDRIVE field.
b0: Override off
b1: RP Override on
11 SENSOR_ACTIVATE_SEL R/W 1 Sensor Activation Mode Selection.
Set the mode for sensor initialization.
b0: Full Current Activation Mode – the LDC will drive maximum sensor current for a shorter sensor activation time.
b1: Low Power Activation Mode – the LDC uses the value programmed in DRIVE_CURRENT_CHx during sensor activation to minimize power consumption.
10 AUTO_AMP_DIS R/W 0 Automatic Sensor Amplitude Correction Disable
Setting this bit will disable the automatic Amplitude correction algorithm and stop the updating of the CHx_INIT_IDRIVE field.
b0: Automatic Amplitude correction enabled
b1: Automatic Amplitude correction is disabled. Recommended for precision applications.
9 REF_CLK_SRC R/W 0 Select Reference Frequency Source b0:
Use Internal oscillator as reference frequency
b1: Reference frequency is provided from CLKIN pin.
8 RESERVED R/W 0 Reserved. Set to b0.
7 INTB_DIS R/W 0 INTB Disable
b0: INTB pin will be asserted when status register updates.
b1: INTB pin will not be asserted when status register updates
6 HIGH_CURRENT_DRV R/W 0 High Current Sensor Drive
b0: The LDC will drive all channels with normal sensor current (1.5mA max).
b1: The LDC will drive channel 0 with current >1.5mA.
This mode is not supported if AUTOSCAN_EN = b1 (multi-channel mode)
5:0 RESERVED R/W 00 0001 Reserved Set to b00’0001

8.6.25 Address 0x1B, MUX_CONFIG

Figure 41. Address 0x1B, MUX_CONFIG
15 14 13 12 11 10 9 8
AUTOSCAN_EN RR_SEQUENCE RESERVED
7 6 5 4 3 2 1 0
RESERVED DEGLITCH
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 36. Address 0x1B, MUX_CONFIG Field Descriptions

Bit Field Type Reset Description
15 AUTOSCAN_EN R/W 0 Auto-Scan Mode Enable
b0: Continuous conversion on the single channel selected by CONFIG.ACTIVE_CHAN register field.
b1: Auto-Scan conversions as selected by MUX_CONFIG.RR_SEQUENCE register field.
14:13 RR_SEQUENCE R/W 00 Auto-Scan Sequence Configuration
Configure multiplexing channel sequence. The LDC will perform a single conversion on each channel in the sequence selected, and then restart the sequence continuously.
b00: Ch0, Ch1
b01: Ch0, Ch1, Ch2 (LDC1314 only)
b10: Ch0, Ch1, Ch2, Ch3 (LDC1314 only)
b11: Ch0, Ch1
12:3 RESERVED R/W 00 0100 0001 Reserved. Must be set to 00 0100 0001
2:0 DEGLITCH R/W 111 Input deglitch filter bandwidth.
Select the lowest setting that exceeds the oscillation tank oscillation frequency.
b001: 1MHz
b100: 3.3MHz
b101: 10MHz
b111: 33MHz

8.6.26 Address 0x1C, RESET_DEV

Figure 42. Address 0x1C, RESET_DEV
15 14 13 12 11 10 9 8
RESET_DEV RESERVED OUTPUT_GAIN RESERVED
7 6 5 4 3 2 1 0
RESERVED
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 37. Address 0x1C, RESET_DEV Field Descriptions

Bit Field Type Reset Description
15 RESET_DEV R/W 0 Device Reset
Write b1 to reset the device. Will always readback 0.
14:11 RESERVED R/W 0000 Reserved. Set to b0000
10:9 OUTPUT_GAIN R/W 00 Output gain control
00: Gain = 1 (0 bits shift)
01: Gain = 4 (2 bits shift)
10: Gain = 8 (3 bits shift)
11: Gain = 16 (4 bits shift)
8:0 RESERVED R/W 0 0000 0000 Reserved, Set to b0 0000 0000

8.6.27 Address 0x1E, DRIVE_CURRENT_CH0

Figure 43. Address 0x1E, DRIVE_CURRENT_CH0
15 14 13 12 11 10 9 8
CH0_IDRIVE CH0_INIT_IDRIVE
7 6 5 4 3 2 1 0
CH0_INIT_IDRIVE RESERVED
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 38. Address 0x1E, DRIVE_CURRENT_CH0 Field Descriptions

Bit Field Type Reset Description
15:11 CH0_IDRIVE R/W 0 0000 Channel 0 L-C Sensor drive current
This field defines the Drive Current used during the settling + conversion time of Channel 0 sensor clock.
RP_OVERRIDE_EN bit must be set to 1.
10:6 CH0_INIT_IDRIVE R 0 0000 Channel 0 Sensor Current Drive
This field stores the Initial Drive Current calculated during the initial Amplitude Calibration phase.
It is updated after each Amplitude Correction phase of the sensor clock if the AUTO_AMP_DIS field is NOT set.
5:0 RESERVED – 00 0000 Reserved

8.6.28 Address 0x1F, DRIVE_CURRENT_CH1

Figure 44. Address 0x1F, DRIVE_CURRENT_CH1
15 14 13 12 11 10 9 8
CH1_IDRIVE CH1_INIT_IDRIVE
7 6 5 4 3 2 1 0
CH1_INIT_IDRIVE RESERVED
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 39. Address 0x1F, DRIVE_CURRENT_CH1 Field Descriptions

Bit Field Type Reset Description
15:11 CH1_IDRIVE R/W 0 0000 Channel 1 L-C Sensor drive current
This field defines the Drive Current used during the settling + conversion time of Channel 1 sensor clock.
RP_OVERRIDE_EN bit must be set to 1.
10:6 CH1_INIT_IDRIVE R 0 0000 Channel 1 Sensor Current Drive
This field stores the Initial Drive Current calculated during the initial Amplitude Calibration phase.
It is updated after each Amplitude Correction phase of the sensor clock if the AUTO_AMP_DIS field is NOT set.
5:0 RESERVED - 00 0000 Reserved

8.6.29 Address 0x20, DRIVE_CURRENT_CH2 (LDC1314 only)

Figure 45. Address 0x20, DRIVE_CURRENT_CH2
15 14 13 12 11 10 9 8
CH2_IDRIVE CH2_INIT_IDRIVE
7 6 5 4 3 2 1 0
CH2_INIT_IDRIVE RESERVED
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 40. Address 0x20, DRIVE_CURRENT_CH2 Field Descriptions

Bit Field Type Reset Description
15:11 CH2_IDRIVE R/W 0 0000 Channel 2 L-C Sensor drive current
This field defines the Drive Current to be used during the settling + conversion time of Channel 2 sensor clock.
RP_OVERRIDE_EN bit must be set to 1.
10:6 CH2_INIT_IDRIVE R 0 0000 Channel 2 Sensor Current Drive
This field stores the Initial Drive Current calculated during the initial Amplitude Calibration phase.
It is updated after each Amplitude Correction phase of the sensor clock if the AUTO_AMP_DIS field is NOT set.
5:0 RESERVED – 00 0000 Reserved

8.6.30 Address 0x21, DRIVE_CURRENT_CH3 (LDC1314 only)

Figure 46. Address 0x21, DRIVE_CURRENT_CH3
15 14 13 12 11 10 9 8
CH3_IDRIVE CH3_INIT_IDRIVE
7 6 5 4 3 2 1 0
CH3_INIT_IDRIVE RESERVED
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 41. DRIVE_CURRENT_CH3 Field Descriptions

Bit Field Type Reset Description
15:11 CH3_IDRIVE R/W 0 0000 Channel 3 L-C Sensor drive current
This field defines the Drive Current to be used during the settling + conversion time of Channel 3 sensor clock.
RP_OVERRIDE_EN bit must be set to 1.
10:6 CH3_INIT_IDRIVE R 0 0000 Channel 3 Sensor Current Drive
This field stores the Initial Drive Current calculated during the initial Amplitude Calibration phase.
It is updated after each Amplitude Correction phase of the sensor clock if the AUTO_AMP_DIS field is NOT set.
5:0 RESERVED – 00 0000 Reserved

8.6.31 Address 0x7E, MANUFACTURER_ID

Figure 47. Address 0x7E, MANUFACTURER_ID
15 14 13 12 11 10 9 8
MANUFACTURER_ID
7 6 5 4 3 2 1 0
MANUFACTURER_ID
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 42. Address 0x7E, MANUFACTURER_ID Field Descriptions

Bit Field Type Reset Description
15:0 MANUFACTURER_ID R 0101 0100 0100 1001 Manufacturer ID = 0x5449

8.6.32 Address 0x7F, DEVICE_ID

Figure 48. Address 0x7F, DEVICE_ID
7 6 5 4 3 2 1 0
DEVICE_ID
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 43. Address 0x7F, DEVICE_ID Field Descriptions

Bit Field Type Reset Description
7:0 DEVICE_ID R 0011 0000 0101 0100 Device ID = 0x3054