SNOSDI7 December   2023 LDC5071-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Diagnostics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Supply Voltage
      2. 6.3.2 Excitation Signal
      3. 6.3.3 Signal Processing Block
        1. 6.3.3.1 Demodulation
        2. 6.3.3.2 Fixed Gain Control
        3. 6.3.3.3 Automatic Gain Control
      4. 6.3.4 Output Stage
      5. 6.3.5 Diagnostics
        1. 6.3.5.1 Undervoltage Diagnostics
        2. 6.3.5.2 Initialization Diagnostics
        3. 6.3.5.3 Normal State Diagnostics
        4. 6.3.5.4 Fault State Diagnostics
    4. 6.4 Device Functional Modes
      1. 6.4.1 IDLE State
      2. 6.4.2 DIAGNOSTICS State
      3. 6.4.3 NORMAL State
      4. 6.4.4 FAULT State
      5. 6.4.5 DISABLED State
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 5-V Supply Mode
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 VREG and VCC
          2. 7.2.1.2.2 Output Capacitors
          3. 7.2.1.2.3 Automatic Gain Control (AGC) Mode
        3. 7.2.1.3 Application Curve
      2. 7.2.2 3.3-V Supply Mode
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
          1. 7.2.2.2.1 VREG and VCC
          2. 7.2.2.2.2 Output Capacitors
          3. 7.2.2.2.3 Fixed Gain Mode
      3. 7.2.3 Redundancy Mode
      4. 7.2.4 Single-Ended Mode
      5. 7.2.5 External Diagnostics Required for Loss of VCC or GND
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Mode 1: VCC = 5 V, VREG = 3.3 V
      2. 7.3.2 Mode 2: VCC = VREG = 3.3 V
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
over recommended Vcc range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input Supply
VCCRamp Allowed VCC ramp up rate 0.17 100e6 V/s
CEXT_VCC External VCC decoupling capacitor range 80 100 nF
Internal LDO Regulator VREG
VVREG Internal LDO output voltage 3.15 3.3 3.6 V
VPOR_VREG_UTH VREG power-on upper threshold 3.15
VPOR_VREG_LTH VREG power-on lower threshold 2.91
ILOAD_REG_EXT Maximum external load on VREG (used for setting voltage on AGC_EN pin externally) (Information Only) 1 mA
ILIM_VREG VREG current limit 40 90
CEXT_VREG External VREG decoupling capacitor 180 2000 nF
Signal Path
ErrINL  Integral Non-Linearity error(3) of the signal path transfer function for each channel measured as:
Maximum % deviation of output from a best fit line through measured outputs when input is swept from minium to maximum value.		 For static inputs; VCC=5V; -3.5V ≤( VOUTxP-VOUTxN) ≤ 3.5V 1% 2.5 %
tPROP_CH  Propagation Delay through receive stage at room temperature. Measured as zero crossing of diffrential input (INx) to zero crossing of differential output (OUTx)
COUT on each pin = 10nF		 3.3 4.6 μs
Propagation Delay through receive stage across temperature (-40℃ to 160℃). 3 5
tPROP_DIFF  Propagation Delay difference between two channels across temperature Measured as delay between the zero crossings of the diffrential outputs. 500 ns
VOUT_SE  Difference between single ended outputs calculated at VOUT0P-VOUT1P Measured for static inputs only for VCC=5V; -1.75V ≤( VOUT0P-VOUT1P) ≤ 1.75V 50 65 mV
VOUT_DIFF Difference between differential output calculated as (VOUT0P-VOUT0N) - (VOUT1P-VOUT1N) at room temperature Measured for static inputs only for VCC=5V; -3.5V ≤( VOUTxP-VOUTxN) ≤ 3.5V 100 mV
VOUT_DIFF_TC  Deviation of VOUT_DIFF at -40℃ from room temperature 20
Deviation of VOUT_DIFF at 160℃ from room temperature 38
GMIS_SIG_PATH  Gain mismatch between Channel 1 and Channel 2 signal path calculated as (Gainout1-Gainout0)/((Gainout1+Gainout0)*0.5)(2) Fixed Gain Mode; VCC=3.3V 4.55%VREG < VAGC_EN < 95.45%VREG
-40℃ ≤ TA ≤ 160°C		 -0.4 0.4 %
Fixed Gain Mode; VCC=5.0V; 4.55%VREG < VAGC_EN < 95.45%VREG
-40℃ ≤ TA ≤ 160°C		 -0.35 0.55
Vin_off  Input referred offset for IN0 channel(2) measured with input shorted and exciter coil connected VCC=3.3V, 5.0V;
Fixed Gain Mode;
30%VREG < VAGC_EN < 95.45%VREG
-40℃ ≤ TA ≤ 160°C		 150 170 µV
Input referred offset for IN1 channel(2) measured with input shorted and exciter coil connected 50 100 µV
nSIG_PATH_SE  Input referred noise for the complete signal path for single ended output for each channel(2) 25 nV/√Hz
nSIG_PATH_DIFF  Input referred noise for the complete signal path for differential output for each channel(2) 36 nV/√Hz
Excitation
VAMP_LC  LC oscillator differential amplitude 3.15V ≤ VVREG ≤ 3.6; TA=25°C 70 75.8 81.5 %Vreg
3.15V ≤ VVREG ≤ 3.6; -40°C < TA < 160°C 64 87
LC oscillator differential amplitude when VVREG is below regulation voltage VPOR_VREG_LTH ≤ VVREG ≤ VPOR_VREG_UTH; TA=25°C 69.5 82.5
VPOR_VREG_LTH ≤ VVREG ≤ VPOR_VREG_UTH; -40°C < TA < 160°C 63 88
VDC_LC  DC operating point for LC oscillator 3.15V ≤ VVREG ≤ 3.6; TA=25°C 47 50 52.5 %VREG
3.15V ≤ VVREG ≤ 3.6; -40°C < TA < 160°C 43.5 56.5
DC operating point for LC oscillator when VVREG is below regulation voltage VPOR_VREG_LTH ≤ VVREG ≤ VPOR_VREG_UTH; TA=25°C 47.5 53
VPOR_VREG_LTH ≤ VVREG ≤ VPOR_VREG_UTH; -40°C < TA < 160°C 42.5 57.5
ILIM_LC RMS value of LC oscillator current limit 13 30 mA
fOSC_LC(2) LC oscillator resonant frequency 2.4 5 MHz
THDLC(2) Total harmonic distortion of oscillator output (VLCIN-VLCOUT) -30 dB
RPU_LCx  Internal pull up resistance to VREG on LCIN and LCOUT pins 220 330 KΩ
RPD_LCx Internal pull down resistance to GND on LCIN and LCOUT pins 220 330 KΩ
Rp Allowed range for equivalent parallel resistance of LC oscillator coil 167 5000 Ω
L Allowed range of inductance of excitation coil resonator 5 μH
CLC1, CLC2 Allowed range for capacitors for excitation coil 100 370 pF
CMIS Allowed capacitor mismatch (between CLC1 and CLC2) -10 10 %
Receiver
VDIFF_REC Allowed range for differential input signal amplitude In fixed gain mode, voltage on AGC_EN pin adjusted to set gain to avoid clipping 5 400 mVp-p
VCOM_REC Common mode voltage forced on input signals 45 50 55 %VREG
fLF_BPF_REC Bandpass filter lower cutoff frequency(1) 430 600 760 kHz
fUF_BPF_REC Bandpass filter upper cutoff frequency(1) 12 20 26 MHz
fLPF_REC Low pass filter (after demodulation) 65 100 125 kHz
VN_DIFF_REC Amplitude of differential noise on input rejected by receive path for fundamental frequency between 10KHz to 20KHz Differential input signal >20mVpp, VCC=5V, Sqaure wave noise signal ramp time = 8µs 1 Vpp
VN_COM_REC Amplitude of common mode noise on input rejected by receive path for fundamental frequency between 10KHz to 20KHz Differential input signal >20mVpp, VCC=5V, Sqaure wave noise signal ramp time = 8µs 1
RPU_INxN Internal pull up resistor to VREG on each of the INxN pins 0.8 1 1.2 MΩ
RPD_INxP Internal pull down resistor to GND on each of the INxP pins 0.8 1 1.2
LREC Typical Receiver coil inductance (Information only) 0.2 μH
RREC Typical Receiver coil resistance (Information only) 6 Ω
Automatic Gain Control
VAGC_EN_AUTO Voltage on AGC_EN pin to set AGC in auto mode 2 %VREG
VAGC_EN_MANUAL Voltage range on AGC_EN pin to manually set  different AGC gains 4.55 95.45
RAGC_EN_MIN Minimum value of required external resistor on AGC_EN to ground to enable AGC mode (Information Only) 1 KΩ
RAGC_EN_MAX Maximum value of required external resistor on AGC_EN to ground to enable AGC mode (Information Only) 16.3 KΩ
RPU_AGC_EN  Internal pull up resistor to VREG on AGC_EN 0.8 1 1.2 MΩ
AGC_Target  Value of √(OUT02 + OUT12) VCC = VCC_33; TA=25°C 54.5 59.5 64.5 %VCC
VCC = VCC_33; -40°C≤TA≤160°C 53.5 65
VCC = VCC_50; TA=25°C 55 60 65
VCC = VCC_50; -40°C≤TA≤160°C 54 66
AGC_FH Automatic gain control - fast regulation region high threshold.  VCC = VCC_33; TA=25°C 75.5 78.9 83 %VCC
VCC = VCC_33; -40°C≤TA≤160°C 75 83.5
VCC = VCC_50; TA=25°C 77 80.1 84
VCC = VCC_50; -40°C≤TA≤160°C 76 85
AGC_SH Automatic gain control - slow regulation region high threshold. VCC = VCC_33; TA=25°C 66 68.8 73.5 %VCC
VCC = VCC_33; -40°C≤TA≤160°C 65.5 74
VCC = VCC_50; TA=25°C 67 70 74
VCC = VCC_50; -40°C≤TA≤160°C 66.5 74.8
AGC_SL Automatic gain control - slow regulation region low threshold.  VCC = VCC_33; TA=25°C 45 48.6 52 %VCC
VCC = VCC_33; -40°C≤TA≤160°C 44.5 52.5
VCC = VCC_50; TA=25°C 46.5 49.8 53
VCC = VCC_50; -40°C≤TA≤160°C 46 53.5
AGC_FL Automatic gain control - fast regulation region low threshold. VCC = VCC_33; TA=25°C 34.5 38.3 42.5 %VCC
VCC = VCC_33; -40°C≤TA≤160°C 34 43
VCC = VCC_50; TA=25°C 36.7 39.9 42.7
VCC = VCC_50; -40°C≤TA≤160°C 36 43.5
Output Stage
VOUT Output signal range OUTxy pins single-ended measurement 7 93 %VCC
VREF_OUT Output reference voltage 48 50 52
IILIM_OUT Current limit source or sink on output pins 3 20 mA
IOUT Load current on output pins 1.5
RPD_OUT  Allowed range for resistor on OUT pins to GND for output pins during a detected fault condition. Refer to VOUT_FLT_LOW for error band 4 20 kΩ
RPU_OUT Allowed range for resistor on OUT pins to VCC for output pin during a detected fault condition. Refer to VOUT_FLT_HIGH for error band 4 20
COUT Capacitors on OUT pins (Information Only) RPD_OUT = RPU_OUT = 10kΩ, 8kHz rotation speed 1 8 nF
COUT Capacitors on OUT pins (Information Only) Maximum rotational speed limited 8 200
ISCB_OUT Short circuit current into OUT pins when shorted to voltage higher than VCC VOUT>8V; VCC=5V 5 mA
IOUT_NOVCC_DIFF  Leakage current in to each OUT pin when VCC is lost; Outputs used in differential mode. VCC pin open; RPU_OUT =5K on each OUTx pin; VCC=3.3V 12 µA
VCC pin open; RPU_OUT =5K on each OUTx pin; VCC=5.0V 25
IOUT_NOVCC_SE Leakage current in to each OUT pin when VCC is lost; Outputs used in single-ended mode. VCC pin open; RPU_OUT =5K on each OUTxP pins; VCC=3.3V 17
VCC pin open; RPU_OUT =5K on each OUTxP pins; VCC=5.0V 35
IOUT_NOGND_DIFF Leakage current out of each OUT pin when GND is lost; Outputs used in differential mode. GND pin open; RPD_OUT = 5K on each OUTx pin; VCC=3.3V 30 µA
GND open; RPD_OUT = 5K on each OUTx pin; VCC=5.0V 50
IOUT_NOGND_SE Leakage current out of each OUT pin when GND is lost; Outputs used in single-ended mode. GND pin open; RPD_OUT = 5K on each OUTxP pin; VCC=3.3V 35
GND pin open; RPD_OUT = 5K on each OUTxP pin; VCC=5.0V 60
VOUT_FLT_LOW  Voltage on OUT pins in fault state with external pulldown resistors to ground on OUT pins 4KΩ ≤ RPD_OUT ≤ 20KΩ on each OUTx pin; VCC=3.3V;5.0V;
-40°C ≤ TA ≤ 160°C		 4 %VCC
VOUT_FLT_HIGH Voltage on OUT pins in fault state with external pullup resistors to VCC on OUT pins 4KΩ ≤ RPU_OUT ≤ 5KΩ on each OUTx pin; VCC=3.3V;
-40°C ≤ TA ≤ 160°C		 96 %VCC
4KΩ ≤ RPU_OUT ≤ 10KΩ on each OUTx pin; VCC=5.0V;
-40°C ≤ TA ≤ 160°C		 96
IOUT_LK_PU Leakge current on OUT pins in fault state with external pullup resistors to VCC on OUT pins when VOUTx > VOUT_FLT_HIGH 5KΩ ≤ RPU_OUT ≤ 20KΩ on each OUTx pin; VCC=3.3V;
-40°C ≤ TA ≤ 160°C		 30 µA
10KΩ ≤ RPU_OUT ≤ 20KΩ on each OUTx pin; VCC=5.0V;
-40°C ≤ TA ≤ 160°C		 20
(1) Guaranteed by design
(2) Not tested in production
(3) This INL error is not same as INL error in calculated angle in the external MCU