SNOSD47C december   2018  – july 2023 LDC5072-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Description (cont.)
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Diagnostics
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Supply Voltage
      2. 8.3.2 Excitation Signal
      3. 8.3.3 Signal Processing Block
        1. 8.3.3.1 Demodulation
        2. 8.3.3.2 Fixed Gain Control
        3. 8.3.3.3 Automatic Gain Control
      4. 8.3.4 Output Stage
      5. 8.3.5 Diagnostics
        1. 8.3.5.1 Undervoltage Diagnostics
        2. 8.3.5.2 Initialization Diagnostics
        3. 8.3.5.3 Normal State Diagnostics
        4. 8.3.5.4 Fault State Diagnostics
    4. 8.4 Device Functional Modes
      1. 8.4.1 IDLE State
      2. 8.4.2 DIAGNOSTICS State
      3. 8.4.3 NORMAL State
      4. 8.4.4 FAULT State
      5. 8.4.5 DISABLED State
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 5-V Supply Mode
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 VREG and VCC
          2. 9.2.1.2.2 Output Capacitors
          3. 9.2.1.2.3 AGC Mode
        3. 9.2.1.3 Application Curve
      2. 9.2.2 3.3-V Supply Mode
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 VREG and VCC
          2. 9.2.2.2.2 Output Capacitors
          3. 9.2.2.2.3 Fixed Gain Mode
      3. 9.2.3 Redundancy Mode
      4. 9.2.4 Single-Ended Mode
      5. 9.2.5 External Diagnostics Required for Loss of VCC or GND
  11. 10Power Supply Recommendations
    1. 10.1 Mode 1: VCC = 5 V, VREG = 3.3 V
    2. 10.2 Mode 2: VCC = VREG = 3.3 V
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.5 External Diagnostics Required for Loss of VCC or GND

The robustness of the system can be improved by implementing simple checks in software. The primary reason for this is to help with the loss of VCC or loss of GND fault condition.

Fault detection is typically done by measuring when the OUTx pins enter a High-Z state. This is done by adding pullup and pulldown resistors on the controller board. The ADC then measures if the OUTx signals ever exceed VOUT_FLT_HIGH or are below VOUT_FLT_LOW.

If a pullup resistor is used, a loss-of-VCC condition on the sensor board causes there to be a small leakage current (IOUT_NOVCC) path into the OUTx pin. If a pulldown resistor is used, a loss of GND condition on the sensor board will have a leakage current path (IOUT_NOGND) into OUTx pin. The leakage current value is controlled such that the OUTx pin voltages stay above VOUT_FLT_HIGH and below VOUT_FLT_LOW. However if certain application conditions cause the OUTx pin voltage outside the fault thresholds, following options is recommended to ensure that the MCU recognizes that a fault has occurred:

  • Use a combination of pullup and pulldown resistors. This way, a loss of ground or loss of VCC will always be detected by two of the four OUTx pins. For example, if a pulldown resistor is present, then a loss of VCC can be signaled with a voltage below VOUT_FLT_LOW. If a pullup resistor is used, then a loss of GND can be signaled with a voltage about VOUT_FLT_HIGH.
  • Track the common-mode voltage of the OUT0x and OUT1x pairs. Normally the common mode will be half of VCC. A loss of VCC or GND is easily caught by using this method. This method does not work when using single-ended mode.