SNOSD47C december   2018  – july 2023 LDC5072-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Description (cont.)
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Diagnostics
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Supply Voltage
      2. 8.3.2 Excitation Signal
      3. 8.3.3 Signal Processing Block
        1. 8.3.3.1 Demodulation
        2. 8.3.3.2 Fixed Gain Control
        3. 8.3.3.3 Automatic Gain Control
      4. 8.3.4 Output Stage
      5. 8.3.5 Diagnostics
        1. 8.3.5.1 Undervoltage Diagnostics
        2. 8.3.5.2 Initialization Diagnostics
        3. 8.3.5.3 Normal State Diagnostics
        4. 8.3.5.4 Fault State Diagnostics
    4. 8.4 Device Functional Modes
      1. 8.4.1 IDLE State
      2. 8.4.2 DIAGNOSTICS State
      3. 8.4.3 NORMAL State
      4. 8.4.4 FAULT State
      5. 8.4.5 DISABLED State
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 5-V Supply Mode
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 VREG and VCC
          2. 9.2.1.2.2 Output Capacitors
          3. 9.2.1.2.3 AGC Mode
        3. 9.2.1.3 Application Curve
      2. 9.2.2 3.3-V Supply Mode
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 VREG and VCC
          2. 9.2.2.2.2 Output Capacitors
          3. 9.2.2.2.3 Fixed Gain Mode
      3. 9.2.3 Redundancy Mode
      4. 9.2.4 Single-Ended Mode
      5. 9.2.5 External Diagnostics Required for Loss of VCC or GND
  11. 10Power Supply Recommendations
    1. 10.1 Mode 1: VCC = 5 V, VREG = 3.3 V
    2. 10.2 Mode 2: VCC = VREG = 3.3 V
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.3.3 Automatic Gain Control

When the voltage on the AGC_EN pin is below VAGC_EN_AUTO, the manual gain control function is disabled and the Automatic Gain Control (AGC) is enabled.

In AGC mode, the device will change the gain of the last stage of the signal processing block to keep the final output within an appropriate voltage range on VOUT. The AGC block uses the square root of the sum of the squared amplitudes of the two channels to sense amplitude of output signals and set gain selection. Both channels will have the same gain. This means that the AGC block will set the gain for sine and cosine channels such that the quantity AGC_TARGET as defined in Equation 8 is within the ranges listed in SpecificationsSpecifications.

Equation 8. GUID-20200922-CA0I-GDKK-4CRT-9NHX7BRPKCFZ-low.gif

where

  • OUTxx: Voltage on the output pins
  • VCC: Voltage on the VCC pin
  • AGC_TARGET: Regulation target for the AGC block

The AGC sets the gain in the DIAGNOSTICS state and then dynamically regulates it in NORMAL state. There are two regions of regulation, the slow AGC regulation region and the fast AGC regulation region. This is shown in Figure 9-10. The blue curve shows the ratio defined by Equation 8 as percentage of VCC. If the ratio rises above AGC_FH or falls below AGC_FL, fast regulation becomes active, and the gain is changed by four gain codes every nominal value of 819.2 μs. If the ratio falls between AGC_SH and AGC_FH, or between AGC_FL and AGC_SL, slow regulation is active, and the gain is changed by one code approximately every 840mS. To allow for faster settling of the output during power up in diagnostic state, the device changes gain by one code every 3.2 μs in slow AGC region and eight codes every 3.2 μs in the fast AGC region. The thresholds are listed in SpecificationsSpecifications. The gain step size is constant in dB scale and is approximately equal to 0.15 dB. Figure 9-10 shows the two cases: a fast change (for example, due to a transient), and a slow change due to lifetime drift.

The AGC block thus will try to compensate for changes in amplitude of the input signal or changes in VCC. If the ratio, after reaching AGC_TARGET, stays between AGC_SH and AGC_SL, then AGC does not react and does not change the gain. The AGC block engages if one of the thresholds is crossed, and it will try to change the output amplitudes such that the ratio reaches AGC_TARGET again. Hence, the No Gain Control region in Figure 9-10 causes the AGC block to have some hysteresis.

GUID-60B940EC-B392-49F9-9D61-21281DC29FA1-low.gifFigure 8-3 AGC Regulation Bands