SNOSBI3C July   2000  – October 2018 LF198-N , LF298 , LF398-N

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Connection
      2.      Acquisition Time
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics, LF198-N and LF298
    5. 6.5 Electrical Characteristics, LF198A-N
    6. 6.6 Electrical Characteristics, LF398-N
    7. 6.7 Electrical Characteristics, LF398A-N (OBSOLETE)
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 TTL and CMOS 3 V ≤ VLOGIC (Hi State) ≤ 7 V
    2. 7.2 CMOS 7 V ≤ VLOGIC (Hi State) ≤ 15 V
    3. 7.3 Operational Amplifier Drive
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Hold Capacitor
      2. 9.1.2 DC and AC Zeroing
      3. 9.1.3 Logic Rise Time
      4. 9.1.4 Sampling Dynamic Signals
      5. 9.1.5 Digital Feedthrough
    2. 9.2 Typical Applications
      1. 9.2.1  X1000 Sample and Hold
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2  Sample and Difference Circuit
      3. 9.2.3  Ramp Generator With Variable Reset Level
      4. 9.2.4  Integrator With Programmable Reset Level
      5. 9.2.5  Output Holds at Average of Sampled Input
      6. 9.2.6  Increased Slew Current
      7. 9.2.7  Reset Stabilized Amplifier
      8. 9.2.8  Fast Acquisition, Low Droop Sample and Hold
      9. 9.2.9  Synchronous Correlator for Recovering Signals Below Noise Level
      10. 9.2.10 2-Channel Switch
      11. 9.2.11 DC and AC Zeroing
      12. 9.2.12 Staircase Generator
      13. 9.2.13 Differential Hold
      14. 9.2.14 Capacitor Hysteresis Compensation
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Electrical Characteristics, LF398A-N (OBSOLETE)

The following specifications apply for –VS + 3.5 V ≤ VIN ≤ +VS – 3.5 V, +VS = +15 V, –VS = –15 V, TA = TJ = 25°C, Ch = 0.01 µF, RL = 10 kΩ, LOGIC REFERENCE = 0 V, LOGIC HIGH = 2.5 V, LOGIC LOW = 0 V unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input offset voltage(1) TJ = 25°C 2 2 mV
Full temperature range 3 mV
Input bias current(1) TJ = 25°C 10 25 nA
Full temperature range 50 nA
Input impedance TJ = 25°C 10 GΩ
Gain error TJ = 25°C, RL = 10 k 0.004% 0.005%
Full temperature range 0.01%
Feedthrough attenuation ratio at 1 kHz TJ = 25°C, Ch = 0.01 µF 86 90 dB
Output impedance TJ = 25°C, “HOLD” mode 0.5 1 Ω
Full temperature range 6 Ω
HOLD step(2) TJ = 25°C, Ch = 0.01 µF, VOUT = 0 1 1 mV
Supply current(1) TJ ≥ 25°C 4.5 6.5 mA
Logic and logic reference input current TJ = 25°C 2 10 µA
Leakage current into hold capacitor(1) TJ = 25°C, hold mode(3) 30 100 pA
Acquisition time to 0.1% ΔVOUT = 10 V, Ch = 1000 pF 4 6 µs
CH = 0.01 µF 20 25 µs
Hold capacitor charging current VIN – VOUT = 2 V 5 mA
Supply voltage rejection ratio VOUT = 0 90 110 dB
Differential logic threshold TJ = 25°C 0.8 1.4 2.4 V
(1) These parameters ensured over a supply voltage range of ±5 to ±18 V, and an input range of –VS + 3.5 V ≤ VIN ≤ +VS – 3.5 V.
(2) Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1 pF, for instance, will create an additional 0.5-mV step with a 5-V logic swing and a 0.01-µF hold capacitor. Magnitude of the hold step is inversely proportional to hold capacitor value.
(3) Leakage current is measured at a junction temperature of 25°C. The effects of junction temperature rise due to power dissipation or elevated ambient can be calculated by doubling the 25°C value for each 11°C increase in chip temperature. Leakage is guaranteed over full input signal range.