SNOSD57 June   2017 LF298-MIL

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 TTL and CMOS 3 V ≤ VLOGIC (Hi State) ≤ 7 V
    2. 7.2 CMOS 7 V ≤ VLOGIC (Hi State) ≤ 15 V
    3. 7.3 Operational Amplifier Drive
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Hold Capacitor
      2. 9.1.2 DC and AC Zeroing
      3. 9.1.3 Logic Rise Time
      4. 9.1.4 Sampling Dynamic Signals
      5. 9.1.5 Digital Feedthrough
    2. 9.2 Typical Applications
      1. 9.2.1  X1000 Sample and Hold
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2  Sample and Difference Circuit
      3. 9.2.3  Ramp Generator With Variable Reset Level
      4. 9.2.4  Integrator With Programmable Reset Level
      5. 9.2.5  Output Holds at Average of Sampled Input
      6. 9.2.6  Increased Slew Current
      7. 9.2.7  Reset Stabilized Amplifier
      8. 9.2.8  Fast Acquisition, Low Droop Sample and Hold
      9. 9.2.9  Synchronous Correlator for Recovering Signals Below Noise Level
      10. 9.2.10 2-Channel Switch
      11. 9.2.11 DC and AC Zeroing
      12. 9.2.12 Staircase Generator
      13. 9.2.13 Differential Hold
      14. 9.2.14 Capacitor Hysteresis Compensation
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Parameter Measurement Information

7.1 TTL and CMOS 3 V ≤ VLOGIC (Hi State) ≤ 7 V

LF298-MIL logic_input_configuration_01_snosbi3.gif
Threshold = 1.4 V
Figure 18. Sample When Logic High With TTL and CMOS Biasing
LF298-MIL logic_input_configuration_02_snosbi3.gif
Threshold = 1.4 V
Select for 2.8 V at pin 8
Figure 19. Sample When Logic Low With TTL and CMOS Biasing

7.2 CMOS 7 V ≤ VLOGIC (Hi State) ≤ 15 V

LF298-MIL logic_input_configuration_03_snosbi3.gif
Threshold = 0.6 (V+) + 1.4 V
Figure 20. Sample When Logic High With CMOS Biasing
LF298-MIL logic_input_configuration_04_snosbi3.gif
Threshold = 0.6 (V+) –1.4V
Figure 21. Sample When Logic Low With CMOS Biasing

7.3 Operational Amplifier Drive

LF298-MIL logic_input_configuration_05_snosbi3.gif
Threshold ≈ +4 V
Figure 22. Sample When Logic High With Operational Amplifier Biasing
LF298-MIL logic_input_configuration_06_snosbi3.gif
Threshold = −4 V
Figure 23. Sample When Logic Low With Operational Amplifier Biasing