The LM10 series are monolithic linear ICs consisting of a precision reference, an adjustable reference buffer and an independent, high-quality operational amplifier.
The unit can operate from a total supply voltage as low as 1.1 V or as high as 40 V, drawing only 270 μA. A complementary output stage swings within 15 mV of the supply terminals or will deliver ±20-mA output current with ±0.4-V saturation. Reference output can be as low as 200 mV.
The circuit is recommended for portable equipment and is completely specified for operation from a single power cell. In contrast, high output-drive capability, both voltage and current, along with thermal overload protection, suggest it in demanding general-purpose applications.
The device is capable of operating in a floating mode, independent of fixed supplies. It can function as a remote comparator, signal conditioner, SCR controller or transmitter for analog signals, delivering the processed signal on the same line used to supply power. It is also suited for operation in a wide range of voltage and current regulator applications, from low voltages to several hundred volts, providing greater precision than existing ICs.
This series is available in the three standard temperature ranges, with the commercial part having relaxed limits. In addition, a low-voltage specification (suffix L) is available in the limited temperature ranges at a cost savings.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LM10 | SOIC (14) | 8.992 mm × 7.498 mm |
SDIP (8) | 8.255 mm × 8.255 mm | |
PDIP (8) | 9.81 mm × 6.35 mm |
Changes from D Revision (March 2013) to E Revision
Changes from C Revision (March 2013) to D Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
Balance | 5 | I | Used for offset nulling |
Op Amp Input (+) | 3 | I | Noninverting input of operational amplifier |
Op Amp Input (–) | 2 | I | Inverting input of operational amplifier |
Op Amp Output | 6 | O | Output terminal of operational amplifier |
Reference Feedback | 8 | I | Feedback terminal of reference |
Reference Output | 1 | O | Output terminal of reference |
V+ | 7 | I | Positive supply voltage |
V– | 4 | I | Negative supply voltage |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
Balance | 9 | I | Used for offset nulling |
NC | 1, 2, 7, 8, 14, 13 | — | No connection |
Op Amp Input (–) | 4 | I | Inverting input of operational amplifier |
Op Amp Input (+) | 5 | I | Noninverting input of operational amplifier |
Op Amp Output | 10 | O | Output terminal of operational amplifier |
Reference Feedback | 12 | I | Feedback terminal of reference |
Reference Output | 3 | O | Output terminal of reference |
V+ | 11 | I | Positive supply voltage |
V– | 6 | I | Negative supply voltage |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Total supply voltage | LM10/LM10B/LM10C | 45 | V | ||
LM10BL/LM10CL | 7 | V | |||
Differential input voltage(2) | LM10/LM10B/LM10C | ±40 | V | ||
LM10BL/LM10CL | ±7 | V | |||
Power dissipation(3) | Internally limited | ||||
Output short-circuit duration(4) | Continuous | ||||
Lead temperature | TO | Soldering (10 seconds) | 300 | °C | |
DIP | Soldering (10 seconds) | 260 | °C | ||
Vapor phase (60 seconds) | 215 | °C | |||
Infrared (15 seconds) | 220 | °C | |||
Maximum junction temperature | LM10 | 150 | °C | ||
LM10B | 100 | °C | |||
LM10C | 85 | °C | |||
Storage temperature, Tstg | −55 | 150 | °C |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VS | Supply input voltage range (V–) – (V+) | 1.2 | 40 | V | |
VCM | Common-mode voltage | (V–) | (V+) – 0.85 | V | |
VREF | Reference voltage | 0.2 | V | ||
IREF | Reference current | 0 | 1 | mA |
THERMAL METRIC(1) | LM10 | UNIT | |||
---|---|---|---|---|---|
NEV (SDIP) | NPA (SOIC) | P (PDIP) | |||
8 PINS | 14 PINS | 8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 150 | 90 | 87 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 45 | — | — | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Input offset voltage | TJ=25°C | 0.3 | 2 | mV | ||
TMIN ≤ TJ ≤ TMAX (see (1)) | 3 | mV | ||||
Input offset current(2) | TJ=25°C | 0.25 | 0.7 | nA | ||
TMIN ≤ TJ ≤ TMAX (see (1)) | 1.5 | nA | ||||
Input bias current | TJ=25°C | 10 | 20 | nA | ||
TMIN ≤ TJ ≤ TMAX (see (1)) | 30 | nA | ||||
Input resistance | TJ=25°C | 250 | 500 | kΩ | ||
TMIN ≤ TJ ≤ TMAX (see (1)) | 150 | kΩ | ||||
Large signal voltage gain | VS = ±20 V, IOUT = 0 | 120 | 400 | V/mV | ||
VOUT = ±19.95 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 80 | V/mV | ||||
VS = ±20 V, VOUT = ±19.4 V | 50 | 130 | V/mV | |||
IOUT = ±20 mA, TMIN ≤ TJ ≤ TMAX (see (1)) | 20 | V/mV | ||||
IOUT = ±15 mA, TMIN ≤ TJ ≤ TMAX (see (1)) | 20 | V/mV | ||||
VS = ±0.6 V, IOUT = ±2 mA | 1.5 | 3 | V/mV | |||
VS = ±0.65 V, IOUT = ±2 mA, TMIN ≤ TJ ≤ TMAX (see (1)) | 1.5 | 3 | V/mV | |||
VOUT = ±0.4 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 0.5 | V/mV | ||||
VOUT = ±0.3 V, VCM = −0.4 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 0.5 | V/mV | ||||
Shunt gain(3) | 1.2 V ≤ VOUT ≤ 40 V, RL = 1.1 kΩ | 14 | 33 | V/mV | ||
1.3 V ≤ VOUT ≤ 40 V, RL = 1.1 kΩ, TMIN ≤ TJ ≤ TMAX (see (1)) | 14 | 33 | V/mV | |||
0.1 mA ≤ IOUT ≤ 5 mA, TMIN ≤ TJ ≤ TMAX (see (1)) | 6 | V/mV | ||||
1.5 V ≤ V+ ≤ 40 V, RL = 250 Ω | 8 | 25 | V/mV | |||
0.1 mA ≤ IOUT ≤ 20 mA, TMIN ≤ TJ ≤ TMAX (see (1)) | 4 | V/mV | ||||
Common-mode rejection | −20 V ≤ VCM ≤ 19.15 V | 93 | 102 | dB | ||
−20 V ≤ VCM ≤ 19 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 93 | 102 | dB | |||
VS = ±20 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 87 | dB | ||||
Supply-voltage rejection | −0.2 V ≥ V− ≥ −39 V | 90 | 96 | dB | ||
V+ = 1 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 84 | dB | ||||
V+ = 1.1 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 84 | dB | ||||
1 V ≤ V+ ≤ 39.8 V | 96 | 106 | dB | |||
1.1 V ≤ V+ ≤ 39.8 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 96 | 106 | dB | |||
V− = −0.2 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 90 | dB | ||||
Offset voltage drift | 2 | μV/°C | ||||
Offset current drift | 2 | pA/°C | ||||
Bias current drift | TC < 100°C | 60 | pA/°C | |||
Line regulation | 1.2 V ≤ VS ≤ 40 V | 0.001 | 0.003 | %/V | ||
1.3 V ≤ VS ≤ 40 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 0.001 | 0.003 | %/V | |||
0 ≤ IREF ≤ 1 mA, VREF = 200 mV, TMIN ≤ TJ ≤ TMAX (see (1)) | 0.006 | %/V | ||||
Load regulation | 0 ≤ IREF ≤ 1 mA | 0.01% | 0.1% | |||
V+− VREF ≥ 1 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 0.15% | |||||
V+− VREF ≥ 1.1 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 0.15% | |||||
Amplifier gain | 0.2 V ≤ VREF ≤ 35 V | TJ=25°C | 50 | 75 | V/mV | |
TMIN ≤ TJ ≤ TMAX (see (1)) | 23 | V/mV | ||||
Feedback sense voltage | TJ=25°C | 195 | 200 | 205 | mV | |
TMIN ≤ TJ ≤ TMAX (see (1)) | 194 | 206 | mV | |||
Feedback current | TJ=25°C | 20 | 50 | nA | ||
TMIN ≤ TJ ≤ TMAX (see (1)) | 65 | nA | ||||
Reference drift | 0.002 | %/°C | ||||
Supply current | TJ=25°C | 270 | 400 | μA | ||
TMIN ≤ TJ ≤ TMAX (see (1)) | 500 | μA | ||||
Supply current change | 1.2 V ≤ VS ≤ 40 V | TJ=25°C | 15 | μA | ||
TMIN ≤ TJ ≤ TMAX (see (1)) | 75 | |||||
1.3 V ≤ VS ≤ 40 V | TJ=25°C | 15 | μA | |||
TMIN ≤ TJ ≤ TMAX (see (1)) | 75 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Input offset voltage | TJ=25°C | 0.5 | 4 | mV | ||
TMIN ≤ TJ ≤ TMAX (see (1)) | 5 | mV | ||||
Input offset current(2) | TJ=25°C | 0.4 | 2 | nA | ||
TMIN ≤ TJ ≤ TMAX (see (1)) | 3 | nA | ||||
Input bias current | TJ=25°C | 12 | 30 | nA | ||
TMIN ≤ TJ ≤ TMAX (see (1)) | 40 | nA | ||||
Input resistance | TJ=25°C | 150 | 400 | kΩ | ||
TMIN ≤ TJ ≤ TMAX (see (1)) | 115 | kΩ | ||||
Large signal voltage gain | VS = ±20 V, IOUT = 0 | 80 | 400 | V/mV | ||
VOUT = ±19.95 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 50 | V/mV | ||||
VS = ±20 V, VOUT = ±19.4 V | 25 | 130 | V/mV | |||
IOUT = ±20 mA, TMIN ≤ TJ ≤ TMAX (see (1)) | 15 | V/mV | ||||
IOUT = ±15 mA, TMIN ≤ TJ ≤ TMAX (see (1)) | 15 | V/mV | ||||
VS = ±0.6 V, IOUT = ±2 mA | 1 | 3 | V/mV | |||
VS = 0.65 V, IOUT = ±2 mA, TMIN ≤ TJ ≤ TMAX (see (1)) | 1 | 3 | V/mV | |||
VOUT = ±0.4 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 0.75 | V/mV | ||||
VOUT = ±0.3 V, VCM = −0.4 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 0.75 | V/mV | ||||
Shunt gain(3) | 1.2 V ≤ VOUT ≤ 40 V, RL = 1.1 kΩ | 10 | 33 | V/mV | ||
1.3 V ≤ VOUT ≤ 40 V, RL = 1.1 kΩ, TMIN ≤ TJ ≤ TMAX (see (1)) | 10 | 33 | V/mV | |||
0.1 mA ≤ IOUT ≤ 5 mA, TMIN ≤ TJ ≤ TMAX (see (1)) | 6 | V/mV | ||||
1.5 V ≤ V+ ≤ 40 V, RL = 250 Ω | 6 | 25 | V/mV | |||
0.1 mA ≤ IOUT ≤ 20 mA, TMIN ≤ TJ ≤ TMAX (see (1)) | 4 | V/mV | ||||
Common-mode rejection | −20 V ≤ VCM ≤ 19.15 V | 90 | 102 | dB | ||
−20 V ≤ VCM ≤ 19 V | 90 | 102 | dB | |||
VS = ±20 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 87 | dB | ||||
Supply-voltage rejection | −0.2 V ≥ V− ≥ −39 V | 87 | 96 | dB | ||
V+ = 1 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 84 | dB | ||||
V+ = 1.1 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 84 | dB | ||||
1 V ≤ V+ ≤ 39.8 V | 93 | 106 | dB | |||
1.1 V ≤ V+ ≤ 39.8 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 93 | 106 | dB | |||
V− = −0.2 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 90 | dB | ||||
Offset voltage drift | 5 | μV/°C | ||||
Offset current drift | 5 | pA/°C | ||||
Bias current drift | TC < 100°C | 90 | pA/°C | |||
Line regulation | 1.2 V ≤ VS ≤ 40 V | 0.001 | 0.008 | %/V | ||
1.3 V ≤ VS ≤ 40 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 0.001 | 0.008 | %/V | |||
0 ≤ IREF ≤ 1 mA, VREF = 200 mV, TMIN ≤ TJ ≤ TMAX (see (1)) | 0.01 | %/V | ||||
Load regulation | 0 ≤ IREF ≤ 1 mA | 0.01% | 0.15% | |||
V+ − VREF ≥ 1 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 0.2% | |||||
V+ − VREF≥ 1.1 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 0.2% | |||||
Amplifier gain | 0.2 V ≤ VREF ≤ 35 V | TJ=25°C | 25 | 70 | V/mV | |
TMIN ≤ TJ ≤ TMAX (see (1)) | 15 | V/mV | ||||
Feedback sense voltage | TJ=25°C | 190 | 200 | 210 | mV | |
TMIN ≤ TJ ≤ TMAX (see (1)) | 189 | 211 | mV | |||
Feedback current | TJ=25°C | 22 | 75 | nA | ||
TMIN ≤ TJ ≤ TMAX (see (1)) | 90 | nA | ||||
Reference drift | 0.003 | %/°C | ||||
Supply current | TJ=25°C | 300 | 500 | μA | ||
TMIN ≤ TJ ≤ TMAX (see (1)) | 570 | μA | ||||
Supply current change | 1.2 V ≤ VS ≤ 40 V | TJ=25°C | 15 | μA | ||
TMIN ≤ TJ ≤ TMAX (see (1)) | 75 | |||||
1.3 V ≤ VS ≤ 40 V | TJ=25°C | 15 | μA | |||
TMIN ≤ TJ ≤ TMAX (see (1)) | 75 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Input offset voltage | TJ=25°C | 0.3 | 2 | mV | ||
TMIN ≤ TJ ≤ TMAX (see (1)) | 3 | mV | ||||
Input offset current(2) | TJ=25°C | 0.1 | 0.7 | nA | ||
TMIN ≤ TJ ≤ TMAX (see (1)) | 1.5 | nA | ||||
Input bias current | TJ=25°C | 10 | 20 | nA | ||
TMIN ≤ TJ ≤ TMAX (see (1)) | 30 | nA | ||||
Input resistance | TJ=25°C | 250 | 500 | kΩ | ||
TMIN ≤ TJ ≤ TMAX (see (1)) | 150 | kΩ | ||||
Large signal voltage gain | VS = ±3.25 V, IOUT = 0 | 60 | 300 | V/mV | ||
VOUT = ±3.2 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 40 | V/mV | ||||
VS = ±3.25 V, IOUT = 10 mA | 10 | 25 | V/mV | |||
VOUT = ±2.75 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 4 | V/mV | ||||
VS = ±0.6 V, IOUT = ±2 mA | 1.5 | 3 | V/mV | |||
VS = 0.65 V, IOUT = ±2 mA, TMIN ≤ TJ ≤ TMAX (see (1)) | 1.5 | 3 | V/mV | |||
VOUT = ±0.4 V, VCM = −0.4 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 0.5 | V/mV | ||||
VOUT = ±0.3 V, VCM = −0.4 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 0.5 | V/mV | ||||
Shunt gain(3) | 1.5 V ≤ V +≤ 6.5 V, RL = 500 Ω | 8 | 30 | V/mV | ||
0.1 mA ≤ IOUT ≤ 10 mA, TMIN ≤ TJ ≤ TMAX (see (1)) | 4 | V/mV | ||||
Common-mode rejection | −3.25 V ≤ VCM ≤ 2.4 V | 89 | 102 | dB | ||
−3.25 V ≤ VCM ≤ 2.25 V, TMIN ≤ TJ ≤ TMAX (see (1)) | ||||||
VS = ±3.25 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 83 | dB | ||||
Supply-voltage rejection | −0.2 V ≥ V− ≥ −5.4 V | 86 | 96 | dB | ||
V+ = 1 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 80 | dB | ||||
V+ = 1.2 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 80 | dB | ||||
1 V ≤ V+ ≤ 6.3 V | 94 | 106 | dB | |||
1.1 V ≤ V+ ≤ 6.3 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 94 | 106 | dB | |||
V−=0.2 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 88 | dB | ||||
Offset voltage drift | 2 | μV/°C | ||||
Offset current drift | 2 | pA/°C | ||||
Bias current drift | 60 | pA/°C | ||||
Line regulation | 1.2 V ≤ VS ≤ 6.5 V | 0.001 | 0.01 | %/V | ||
1.3 V ≤ VS ≤ 6.5 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 0.001 | 0.01 | %/V | |||
0 ≤ IREF ≤ 0.5 mA, VREF = 200 mV, TMIN ≤ TJ ≤ TMAX (see (1)) | 0.02 | %/V | ||||
Load regulation | 0 ≤ IREF ≤ 0.5 mA | 0.01% | 0.1% | |||
V+ − VREF ≥ 1 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 0.15% | |||||
V+− VREF ≥ 1.1 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 0.15% | |||||
Amplifier gain | 0.2 V ≤ VREF ≤ 5.5 V | TJ=25°C | 30 | 70 | V/mV | |
TMIN ≤ TJ ≤ TMAX (see (1)) | 20 | V/mV | ||||
Feedback sense voltage | TJ=25°C | 195 | 200 | 205 | mV | |
TMIN ≤ TJ ≤ TMAX (see (1)) | 194 | 206 | mV | |||
Feedback current | TJ=25°C | 20 | 50 | nA | ||
TMIN ≤ TJ ≤ TMAX (see (1)) | 65 | nA | ||||
Reference drift | 0.002 | %/°C | ||||
Supply current | TJ=25°C | 260 | 400 | μA | ||
TMIN ≤ TJ ≤ TMAX (see (1)) | 500 | μA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Input offset voltage | TJ=25°C | 0.5 | 4 | mV | ||
TMIN ≤ TJ ≤ TMAX (see (1)) | 5 | mV | ||||
Input offset current(2) | TJ=25°C | 0.2 | 2 | nA | ||
TMIN ≤ TJ ≤ TMAX (see (1)) | 3 | nA | ||||
Input bias current | TJ=25°C | 12 | 30 | nA | ||
TMIN ≤ TJ ≤ TMAX (see (1)) | 40 | nA | ||||
Input resistance | TJ=25°C | 150 | 400 | kΩ | ||
TMIN ≤ TJ ≤ TMAX (see (1)) | 115 | kΩ | ||||
Large signal voltage gain | VS = ±3.25 V, IOUT = 0 | 40 | 300 | V/mV | ||
VOUT = ±3.2 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 25 | V/mV | ||||
VS = ±3.25 V, IOUT = 10 mA | 5 | 25 | V/mV | |||
VOUT = ±2.75 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 3 | V/mV | ||||
VS = ±0.6 V, IOUT = ±2 mA | 1 | 3 | V/mV | |||
VS = 0.65 V, IOUT = ±2 mA, TMIN ≤ TJ ≤ TMAX (see (1)) | 1 | 3 | V/mV | |||
VOUT = ±0.4 V, VCM = −0.4 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 0.75 | V/mV | ||||
VOUT = ±0.3 V, VCM = −0.4 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 0.75 | V/mV | ||||
Shunt gain(3) | 1.5 V ≤ V+ ≤ 6.5 V, RL= 500 Ω | 6 | 30 | V/mV | ||
0.1 mA ≤ IOUT ≤ 10 mA, TMIN ≤ TJ ≤ TMAX (see (1)) | 4 | V/mV | ||||
Common-mode rejection | −3.25 V ≤ VCM ≤ 2.4 V | 80 | 102 | dB | ||
−3.25 V ≤ VCM ≤ 2.25 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 80 | 102 | dB | |||
VS = ±3.25 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 74 | dB | ||||
Supply-voltage rejection | −0.2 V ≥ V– ≥ −5.4 V | 80 | 96 | dB | ||
V+ = 1 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 74 | dB | ||||
V+ = 1.2 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 74 | dB | ||||
1 V ≤ V+ ≤ 6.3 V | 80 | 106 | dB | |||
1.1 V ≤ V+ ≤ 6.3 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 80 | 106 | dB | |||
V− = 0.2 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 74 | dB | ||||
Offset voltage drift | 5 | μV/°C | ||||
Offset current drift | 5 | pA/°C | ||||
Bias current drift | 90 | pA/°C | ||||
Line regulation | 1.2 V ≤ VS ≤ 6.5 V | 0.001 | 0.02 | %/V | ||
1.3 V ≤ VS ≤ 6.5 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 0.001 | 0.02 | %/V | |||
0 ≤ IREF ≤ 0.5 mA, VREF = 200 mV, TMIN ≤ TJ ≤ TMAX (see (1)) | 0.03 | %/V | ||||
Load regulation | 0 ≤ IREF ≤ 0.5 mA | 0.01% | 0.15% | |||
V+− VREF ≥ 1 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 0.2% | |||||
V+− VREF ≥ 1.1 V, TMIN ≤ TJ ≤ TMAX (see (1)) | 0.2% | |||||
Amplifier gain | 0.2 V ≤ VREF ≤ 5.5 V | TJ=25°C | 20 | 70 | V/mV | |
TMIN ≤ TJ ≤ TMAX (see (1)) | 15 | V/mV | ||||
Feedback sense voltage | TJ=25°C | 190 | 200 | 210 | mV | |
TMIN ≤ TJ ≤ TMAX (see (1)) | 189 | 211 | mV | |||
Feedback current | TJ=25°C | 22 | 75 | nA | ||
TMIN ≤ TJ ≤ TMAX (see (1)) | 90 | nA | ||||
Reference drift | 0.003 | %/°C | ||||
Supply current | TJ=25°C | 280 | 500 | μA | ||
TMIN ≤ TJ ≤ TMAX (see (1)) | 570 | μA |
The LM10 is a dual-operational amplifier combined with a voltage reference capable of a single-supply operation down to 1.1 V. It provides high overall performance, making it ideal for many general-purpose applications. The circuit can also operate in a floating mode, powered by residual voltage, independent of fixed supplies and it is well-protected from temperature drift.
The LM10 is specified for operation from 1.2 V to 40 V. Many of the specifications apply from –55⁰C to 125⁰C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in electrical characteristics tables under Specifications and in the Typical Characteristics section.
The input common-mode voltage range of the LM10 extends from the negative rail to 0.85 V less than the positive rail.
The minimum operating voltage is reduced to nearly one volt and the current gain is less affected by temperature, resulting in a fairly flat bias current over temperature.
Second-order nonlinearities are compensated for which eliminates the bowed characteristics of conventional designs, resulting in better temperature stability.
To use the device in a floating mode, the operational amplifier output is shorted to V+ which disables the PNP portion of the output stage. Thus, with a positive input signal, neither halves of the output conducts and the current between the supply terminals is equal to the quiescent supply current. With negative input signals, the NPN portion of the output begins to turn on, reaching the short circuit current for a few hundred microvolts overdrive.
This device can also operate linearly while in the floating mode. An example of this is shown in the Typical Application section.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
With heavy amplifier loading to V−, resistance drops in the V− lead can adversely affect reference regulation. Lead resistance can approach 1 Ω. Therefore, the common to the reference circuitry should be connected as close as possible to the package.
Table 1 lists the design parameters for this example.
DESIGN PARAMETERS | EXAMPLE VALUE | |||
---|---|---|---|---|
Ambient Temperature Range | –55⁰C to 125⁰C | |||
Supply Voltage Range | 1.2 V to 40 V | |||
Common-Mode Input Range | (V–) to (V+) – 0.85 V |
Given that the transfer function of this circuit is:
the output can be set between 0.2 V and the breakdown voltage of the IC by selecting an appropriate value for R2. The circuit regulates for input voltages within a saturation drop of the output (typically 0.4 V at 20 mA and 0.15 V at 5 mA). The regulator is protected from shorts or overloads by current limiting and thermal shutdown.
Typical regulation is about 0.05% load and 0.003%/V line. A substantial improvement in regulation can be effected by connecting the operational amplifier as a follower and setting the reference to the desired output voltage. This has the disadvantage that the minimum input-output differential is increased to a little more than a diode drop. If the operational amplifier were connected for a gain of 2, the output could again saturate. But this requires an additional pair of precision resistors.
The regulator in Figure 36 could be made adjustable to zero by connecting the operational amplifier to a potentiometer on the reference output. This has the disadvantage that the regulation at the lower voltage settings is not as good as it might otherwise be.
Circuit descriptions available in application note AN-211 (SNOA638).
The LM10 is specified for operation from 1.2 V to 40 V unless otherwise stated. Many specifications apply from –55⁰C to 125⁰C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in the Specifications section.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the Absolute Maximum Ratings table.
For best operational performance of the device, good printed-circuit board (PCB) layout practices are recommended. Low-loss, 0.1-uF bypass capacitors should be connected between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable to single-supply applications.
For related documentation, see the following:
AN-211 New Op Amp Ideas, SNOA638
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
SLYZ022 — TI Glossary.
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No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use.
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TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
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