SNVS999 May   2014 LM10507

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Handling Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  General Electrical Characteristics
    6. 7.6  Buck 1 Electrical Characteristics
    7. 7.7  Buck 2 Electrical Characteristics
    8. 7.8  Buck 3 Electrical Characteristics
    9. 7.9  LDO Electrical Characteristics
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Buck Regulators Operation
      2. 8.3.2 Buck Regulators Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 PWM Operation
      2. 8.4.2 PFM Operation (Bucks 1, 2 & 3)
      3. 8.4.3 Soft Start
      4. 8.4.4 Current Limiting
      5. 8.4.5 Internal Synchronous Rectification
      6. 8.4.6 Low Dropout Operation
      7. 8.4.7 Device Operating Modes
        1. 8.4.7.1  Startup Sequence
        2. 8.4.7.2  Power-On Default and Device Enable
        3. 8.4.7.3  RESET: Pin Function
        4. 8.4.7.4  DEVSLP (Device Sleep) Function
        5. 8.4.7.5  DEVSLP Terminal
        6. 8.4.7.6  Device Sleep (DEVSLP) Programming via SPI
        7. 8.4.7.7  ENABLE, Function
        8. 8.4.7.8  Under Voltage Lock Out (UVLO)
        9. 8.4.7.9  Over Voltage Lock Out (OVLO)
        10. 8.4.7.10 PWR_OK - Pin Function
        11. 8.4.7.11 Thermal Shutdown (TSD)
    5. 8.5 Programming
      1. 8.5.1 SPI Data Interface
    6. 8.6 Register Maps
      1. 8.6.1 Registers Configurable Via The SPI Interface
        1. 8.6.1.1 ADDR 0x07 & 0x08: Buck 1 and Buck 2 Voltage Code and VOUT Level Mapping
        2. 8.6.1.2 ADDR 0x00 Buck 3 Voltage Code and VOUT Level Mapping
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Input Voltage
        2. 9.2.2.2  Output Enable
        3. 9.2.2.3  Recommendations for Unused Functions and Pins
        4. 9.2.2.4  External Components Selection
        5. 9.2.2.5  Output Inductors and Capacitors Selection
        6. 9.2.2.6  Inductor Selection
        7. 9.2.2.7  Recommended Method for Inductor Selection
        8. 9.2.2.8  Alternate Method for Inductor Selection
        9. 9.2.2.9  Suggested Inductors and Their Suppliers
        10. 9.2.2.10 Output and Input Capacitors Characteristics
        11. 9.2.2.11 Output Capacitor Selection
        12. 9.2.2.12 Input Capacitor Selection
      3. 9.2.3 Application Performance Plots
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layout Thermal Dissipation for DSBGA Package
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

LM10507 is a highly efficient and integrated Power Management Unit for Systems-on-a-Chip (SoCs), ASICs, and processors. It operates cooperatively and communicates with processors over an SPI interface with output Voltage programmability and Standby Mode. The device incorporates three high-efficiency synchronous buck regulators and one LDO that deliver four output voltages from a single power source. The device also includes a SPI-programmable Comparator Block that provides an interrupt output signal

8.2 Functional Block Diagram

30166204.gif

8.3 Feature Description

8.3.1 Buck Regulators Operation

A buck converter contains a control block, a switching PFET connected between input and output, a synchronous rectifying NFET connected between the output and ground and a feedback path. The following figure shows the block diagram of each of the three buck regulators integrated in the device.

30166208.gifFigure 6. Buck Functional Diagram

During the first portion of each switching cycle, the control block turns on the internal PFET switch. This allows current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of (VIN – VOUT)/L by storing energy in a magnetic field. During the second portion of each cycle, the control block turns the PFET switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of (–VOUT)/L.

The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage across the load. The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and synchronous rectifier at the SW pinto a low-pass filter formed by the inductor and output filter capacitor. The output voltage is equal to the average voltage at the SW terminal.

8.3.2 Buck Regulators Description

The LM10507 incorporates three high-efficiency synchronous switching buck regulators that deliver various voltages from a single DC input voltage. They include many advanced features to achieve excellent voltage regulation, high efficiency and fast transient response time. The bucks feature voltage mode architecture with synchronous rectification.

Each of the switching regulators is specially designed for high-efficiency operation throughout the load range. With a 2MHz typical switching frequency, the external L- C filter can be small and still provide very low output voltage ripple. The bucks are internally compensated to be stable with the recommended external inductors and capacitors as detailed in the application diagram. Synchronous rectification yields high efficiency for low voltage and high output currents.

All bucks can operate up to a 100% duty cycle allowing for the lowest possible input voltage that still maintains the regulation of the output. The lowest input to output dropout voltage is achieved by keeping the PMOS switch on.

Additional features include soft-start, undervoltage lockout, bypass, and current and thermal overload protection. To reduce the input current ripple, the device employs a control circuit that operates the 3 bucks at 120° phase. These bucks are nearly identical in performance and mode of operation. They can operate in FPWM (forced PWM) or automatic mode (PWM/PFM).

8.4 Device Functional Modes

8.4.1 PWM Operation

During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional to the input voltage. To eliminate this dependence, a feed forward voltage inversely proportional to the input voltage is introduced.

In Forced PWM Mode the bucks always operate in PWM mode regardless of the output current.

In Automatic Mode, if the output current is less than 70 mA (typ.), the bucks automatically transition into PFM (Pulse Frequency Modulation) operation to reduce the current consumption. At higher than 70 mA (typ.) they operate in PWM mode. This increases the efficiency at lower output currents.

30166209.gifFigure 7. PFM vs PWM Operation

8.4.2 PFM Operation (Bucks 1, 2 & 3)

At very light loads, Bucks 1, 2, and Buck 3 enter PFM mode and operate with reduced switching frequency and supply current to maintain high efficiency.

Bucks 1, 2 and 3 will automatically transition into PFM mode when either of two conditions occurs for a duration of 32 or more clock cycles:

  1. The inductor current becomes discontinuous, or
  2. The peak PMOS switch current drops below the IMODE level.

During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy load. The PFM comparators sense the output voltage via the feedback pinand control the switching of the output FETs such that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal PWM output voltage. If the output voltage is below the ‘high’ PFM comparator threshold, the PMOS power switch is turned on. It remains on until the output voltage exceeds the ‘high’ PFM threshold or the peak current exceeds the IPFM level set for PFM mode.

Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output voltage is below the ‘high’ PFM comparator threshold (see Figure 7), the PMOS switch is again turned on and the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this ‘idle’ mode is less than 100 µA, which allows the part to achieve high efficiencies under extremely light load conditions. When the output drops below the ‘low’ PFM threshold, the cycle repeats to restore the output voltage to ~1.6% above the nominal PWM output voltage.

If the load current should increase during PFM mode causing the output voltage to fall below the ‘low2’ PFM threshold, the part will automatically transition into fixed-frequency PWM mode.

8.4.3 Soft Start

Each of the buck converters has an internal soft-start circuit that limits the in-rush current during startup. This allows the converters to gradually reach the steady-state operating point, thus reducing startup stresses and surges. During startup, the switch current limit is increased in steps.

For Bucks 1, 2 and 3 the soft start is implemented by increasing the switch current limit in steps that are gradually set higher. The startup time depends on the output capacitor size, load current and output voltage. Typical startup time with the recommended output capacitor of 10 µF is 0.1-0.5ms. It is expected that in the final application the load current condition will be more likely in the lower load current range during the startup.

8.4.4 Current Limiting

A current limit feature protects the device and any external components during overload conditions. In PWM mode the current limiting is implemented by using an internal comparator that trips at current levels according to the buck capability. If the output is shorted to ground the device enters a timed current limit mode where the NFET is turned on for a longer duration until the inductor current falls below a low threshold, ensuring inductor current has more time to decay, thereby preventing runaway.

8.4.5 Internal Synchronous Rectification

While in PWM mode, the bucks use an internal NFET as a synchronous rectifier to reduce the rectifier forward voltage drop and the associated power loss. Synchronous rectification provides a significant improvement in efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier diode.

8.4.6 Low Dropout Operation

The device can operate at 100% duty cycle (no switching; PMOS switch completely on) for low dropout support. In this way the output voltage will be controlled down to the lowest possible input voltage. When the device operates near 100% duty cycle, output voltage ripple is approximately 25 mV.

The minimum input voltage needed to support the output voltage:

Equation 1.

where

  • ILOAD : Load Current
  • RDSON_PFET : Drain to source resistance of PFET (high side)
  • RIND : Inductor resistance

8.4.7 Device Operating Modes

8.4.7.1 Startup Sequence

Once VVIN reaches the UVLO threshold and the ENABLE pin= High the LM10507 will start up. There is a fixed delay of approx. 1 ms before the LDO starts up, followed by Buck1 at 1ms. After a delay of 1msec from Buck1, Buck2 and Buck3 regulators start together. There is a maximum of 500us soft-start with full load for the Bucks

The Startup Sequence will be:

  1. 2.5ms delay after ENABLE.
  2. LDO -> 2.5 V,
  3. 2ms delay.
  4. Buck1 -> 1.8 V, Buck2 -> 1.8 V, Buck3 -> 1.5 V
  5. PWR_OK goes high
operatingmodes.gifFigure 8. Normal Operating Mode

8.4.7.2 Power-On Default and Device Enable

The device will be enabled over the ENABLE terminal, unless outside of operating voltage range. Once VVIN reaches a minimum required input Voltage and ENABLE=High the power-up sequence will be started. Once the device is started, the output voltage of the Bucks can be individually disabled by accessing their corresponding BK1EN, BK2EN register bits (BUCK CONTROL).

8.4.7.3 RESET: Pin Function

The RESET pinis internally pulled up. If the RESET pinis set low, the device will perform a complete reset of all the registers to their default states. This means that all of the voltage settings on the regulators will go back to their default state and all Regulators will be turned ON. All Registers will be set back to default instantaneously but no Start-Up Sequence initiated like it would be with ENABLE terminal.

8.4.7.4 DEVSLP (Device Sleep) Function

The Device can be programmed into Standby mode. There are 2 ways for doing that:

  1. DEVSLP terminal
  2. Programming via SPI

8.4.7.5 DEVSLP Terminal

When the DEVSLP pinis asserted high, the LM10507 will enter Device Sleep Mode. While in Device Sleep Mode, all Regulator outputs are turned OFF except Buck3. Note: Bucks1,2 and LDO will turn off when the DEVSLP signal is given. All disabled output Rails will turn off immediately and at the same time (no sequencing). An internal 22 kΩ (typ.) pull down resistor is attached to the FB pinof Buck 1 and Buck2. Buck 1 and 2 outputs are pulled to ground level when they are disabled to discharge any residual charge present in the output circuitry. When Device Sleep transitions to a low, Buck 1, Buck2 and LDO are enabled. Buck 3 will go back to its previous state

8.4.7.6 Device Sleep (DEVSLP) Programming via SPI

There is no bit which has the same function as DEVSLP terminal. Disabling or programming the Bucks to new level is the user’s decision based on power consumption and other requirements

The following section describes how to program the chip into Device Sleep Mode corresponding to DEVSLP pinfunction: Buck 3 must be PFM. To program the LM10507 to Device Sleep Mode via SPI, Buck 1 and Buck2 must be disabled by host device (Register 0x0A bit 0). The LDO must be disabled (Register 0x0B bit 1 and 0). Then stop the oscillator (Register 0x0E bit 1) To wake LM10507 from Device Sleep Mode, reverse this sequence.

8.4.7.7 ENABLE, Function

The ENABLE pinis a digital function to control the Start-Up of PMIC. ENABLE has an internal pull-down and is active High. A pull-down resistor is connected to GND. Transitions of the ENABLE pinto Low during device operation will disable all regulators and actively force down all the output voltages. Register defaults are restored while ENABLE is low.

8.4.7.8 Under Voltage Lock Out (UVLO)

The VIN voltage is monitored for a supply under voltage condition, for which the operation of the device cannot be guaranteed. The part will automatically disable PMIC. To prevent unstable operation, the UVLO has a hysteresis window of about 300mV. An under voltage lockout (UVLO) will disable all buck outputs, all internal registers are reset. Once the supply voltage is above the UVLO hysteresis, the device will initiate a power-up sequence and then enter the active state.

The LDO will remain functional past the UVLO threshold until VVIN reaches approximately 2.25V.

8.4.7.9 Over Voltage Lock Out (OVLO)

The VIN voltage is monitored for a supply over voltage condition, for which the operation of the device cannot be guaranteed. The purpose of OVLO is to protect the part and all other components connected to the PMU outputs from any damage and malfunction. Once VVIN rises over about 5.8V all the Bucks and LDO will be disabled automatically. To prevent unstable operation, the OVLO has a hysteresis window of about 100mV. An over voltage lockout (OVLO) will force the device into the reset state, all internal registers are reset. Once the supply voltage goes below the OVLO lower threshold, the device will initiate a power-up sequence and then enter the active state. Operating maximum input voltage at which parameters are guaranteed is 5.5 V. Absolute maximum of the device is 6.0 V.

8.4.7.10 PWR_OK – Pin Function

The LM10507 has PWR_OK pinto signal that all output rails are valid. PWR_OK is Low if Buck3 is disabled in register0x0A. If PWR_OK condition is detected, then the Hardware PWR_OK pinwill be set immediately. There are four PWR_OK generating conditions, all must be fulfilled :

  • Buck 3 output is over flag level (90% when rising,85% when falling).
  • Buck 2 output is over flag level (90% when rising,85% when falling) , but not applicable if disabled in register 0x0A.
  • Buck 1 output is over flag level (90% when rising,85% when falling) , but not applicable if disabled in register 0x0A
  • LDO output is over flag level (90% when rising,85% when falling) , but not applicable if disabled in register 0x0B.

NOTE

SPI commanded Disable of any output, followed by a subsequent SPI commanded ENABLE will cause a temporary logic LOW of the PWR_OK pinuntil that Buck output voltage has risen back to the 90% flag level.

8.4.7.11 Thermal Shutdown (TSD)

The temperature of the silicon die is monitored for an over-temperature condition, for which the operation of the device cannot be guaranteed. The part will automatically be disabled if the temperature is too high. The thermal shutdown (TSD) will force the device into the reset state. In reset, all circuitry is disabled. To prevent unstable operation, the TSD has a hysteresis window of about 20۫°C. Once the temperature has decreased below the TSD hysteresis, the device will initiate a power-up sequence and then enter the active state. In the active state, the part will start up as if for the first time, all registers will be in their default state.

8.5 Programming

8.5.1 SPI Data Interface

The device is programmable via 4-wire SPI Interface. The signals associated with this interface are CS, DI, DO and CLK. Through this interface, the user can enable/disable the device, program the output voltages of the individual bucks and of course read the status of Flag registers.

By accessing the registers in the device through this interface, the user can get access and control the operation of the buck controllers and program the reference voltage of the comparator in the device.

30166210.gifFigure 9. SPI Interface Write
  • Data In (DI)
    • 1 to 0 Write Command
    • A4to A0 Register address to be written
    • D7 to D0 Data to be written
  • Data Out (DO)
    • All Os
30166227.gifFigure 10. SPI Interface Read
  • Data In (DI)
    • 1 to 1 Read Command
    • A4to A0 Register address to be read
  • Data Out (DO)
    • D7 to D0 Data Read

8.6 Register Maps

8.6.1 Registers Configurable Via The SPI Interface

Addr Reg Name Bit R/W Default Description Notes
0x00 Buck 3 Voltage 7 — — Reset default:
0x7F (1.5 V)
6 R/W 1 Buck 3 Voltage Code[6] Range: 0.865-1.5 V
5 R/W 1 Buck 3 Voltage Code[5]
4 R/W 1 Buck 3 Voltage Code[4]
3 R/W 1 Buck 3 Voltage Code[3]
2 R/W 1 Buck 3 Voltage Code[2]
1 R/W 1 Buck 3 Voltage Code[1]
0 R/W 1 Buck 3 Voltage Code[0]
0x07 Buck 1 Voltage 7 — — — Reset default:
6 — — 0x12 (1.8 V)
5 R/W 0 Buck 1 Voltage Code[5]
4 R/W 1 Buck 1 Voltage Code[4] Range: 0.9-3.4
3 R/W 0 Buck 1 Voltage Code[3]
2 R/W 0 Buck 1 Voltage Code[2]
1 R/W 1 Buck 1 Voltage Code[1]
0 R/W 0 Buck 1 Voltage Code[0]
0x08 Buck 2 Voltage 7 — — — Reset default:
6 — — — 0x12 (1.8 V)
5 R/W 0 Buck 2 Voltage Code[5]
4 R/W 1 Buck 2 Voltage Code[4] Range: 0.9-3.4
3 R/W 0 Buck 2 Voltage Code[3]
2 R/W 0 Buck 2 Voltage Code[2]
1 R/W 1 Buck 2 Voltage Code[1]
0 R/W 0 Buck 2 Voltage Code[0]
0x09 DevSLP Mode Voltage for Buck 3 7 R/W — — Reset default:
6 R/W 1 Buck 3 Voltage Code[6] 0x7F (1.5 V)
5 R/W 1 Buck 3 Voltage Code[5]
4 R/W 1 Buck 3 Voltage Code[4]
3 R/W 1 Buck 3 Voltage Code[3]
2 R/W 1 Buck 3 Voltage Code[2]
1 R/W 1 Buck 3 Voltage Code[1]
0 R/W 1 Buck 3 Voltage Code[0]
0x0A Buck Control 7 R/W 1 BK3EN Enable/Disable Buck 3
6 — — —
5 — — —
4 R/W — BK1FPWM Buck 1 forced PWM mode when high
3 R/W 0 BK2FPWM Buck 2 forced PWM mode when high
2 R/W 0 BK3FPWM Buck 3 forced PWM mode when high
1 R/W 1 BK1EN Enables Buck 1 0-disabled, 1-enabled
0 R/W 1 BK2EN Enables Buck 2 0-disabled, 1-enabled
0x0B LDO Control 7 — — —
6 — — —
5 — — —
4 — — —
3 — — —
2 — — —
1 — — —
0 R/W 1 LDO Enable
0x0D Status 7 —
6 —
5 —
4 R LDO OK LDO is greater than 90% of target
3 R Buck 3 OK Buck 3 is greater than 90% of target
2 R Buck 2 OK Buck 2 is greater than 90% of target
1 R Buck 1 OK Buck 1 is greater than 90% of target
0 R PWR_OK PWR_OK output is high
0x0E MISC Control 7 —
6 —
5 —
4 —
3 —
2 —
1 R/W 0 Oscillator Disable OSC ENABLE/DISABLE
0

8.6.1.1 ADDR 0x07 & 0x08: Buck 1 and Buck 2 Voltage Code and VOUT Level Mapping

Voltage Code Voltage Voltage Code Voltage
0x00 0.9 0x20 2.5
0x01 0.95 0x21 2.55
0x02 1 0x22 2.6
0x03 1.05 0x23 2.65
0x04 1.1 0x24 2.7
0x05 1.15 0x25 2.75
0x06 1.2 0x26 2.8
0x07 1.25 0x27 2.85
0x08 1.3 0x28 2.9
0x09 1.35 0x29 2.95
0x0A 1.4 0x2A 3
0x0B 1.45 0x2B 3.05
0x0C 1.5 0x2C 3.1
0x0D 1.55 0x2D 3.15
0x0E 1.6 0x2E 3.2
0x0F 1.65 0x2F 3.25
0x10 1.7 0x30 3.3
0x11 1.75 0x31 3.35
0x12 1.8 0x32 3.4
0x13 1.85 0x33 3.4
0x14 1.9 0x34 3.4
0x15 1.95 0x35 3.4
0x16 2 0x36 3.4
0x17 2.05 0x37 3.4
0x18 2.1 0x38 3.4
0x19 2.15 0x39 3.4
0x1A 2.2 0x3A 3.4
0x1B 2.25 0x3B 3.4
0x1C 2.3 0x3C 3.4
0x1D 2.35 0x3D 3.4
0x1E 2.4 0x3E 3.4
0x1F 2.45 0x3F 3.4

8.6.1.2 ADDR 0x00 Buck 3 Voltage Code and VOUT Level Mapping

Voltage Code Voltage Voltage Code Voltage Voltage Code Voltage Voltage Code Voltage
0x00 0.865 0x20 1.025 0x40 1.185 0x60 1.345
0x01 0.87 0x21 1.03 0x41 1.19 0x61 1.35
0x02 0.875 0x22 1.035 0x42 1.195 0x62 1.355
0x03 0.88 0x23 1.04 0x43 1.2 0x63 1.36
0x04 0.885 0x24 1.045 0x44 1.205 0x64 1.365
0x05 0.89 0x25 1.05 0x45 1.21 0x65 1.37
0x06 0.895 0x26 1.055 0x46 1.215 0x66 1.375
0x07 0.9 0x27 1.06 0x47 1.22 0x67 1.38
0x08 0.905 0x28 1.065 0x48 1.225 0x68 1.385
0x09 0.91 0x29 1.07 0x49 1.23 0x69 1.39
0x0A 0.915 0x2A 1.075 0x4A 1.235 0x6A 1.395
0x0B 0.92 0x2B 1.08 0x4B 1.24 0x6B 1.4
0x0C 0.925 0x2C 1.085 0x4C 1.245 0x6C 1.405
0x0D 0.93 0x2D 1.09 0x4D 1.25 0x6D 1.41
0x0E 0.935 0x2E 1.095 0x4E 1.255 0x6E 1.415
0x0F 0.94 0x2F 1.1 0x4F 1.26 0x6F 1.42
0x10 0.945 0x30 1.105 0x50 1.265 0x70 1.425
0x11 0.95 0x31 1.11 0x51 1.27 0x71 1.43
0x12 0.955 0x32 1.115 0x52 1.275 0x72 1.435
0x13 0.96 0x33 1.12 0x53 1.28 0x73 1.44
0x14 0.965 0x34 1.125 0x54 1.285 0x74 1.445
0x15 0.97 0x35 1.13 0x55 1.29 0x75 1.45
0x16 0.975 0x36 1.135 0x56 1.295 0x76 1.455
0x17 0.98 0x37 1.14 0x57 1.3 0x77 1.46
0x18 0.985 0x38 1.145 0x58 1.305 0x78 1.465
0x19 0.99 0x39 1.15 0x59 1.31 0x79 1.47
0x1A 0.995 0x3A 1.155 0x5A 1.315 0x7A 1.475
0x1B 1 0x3B 1.16 0x5B 1.32 0x7B 1.48
0x1C 1.005 0x3C 1.165 0x5C 1.325 0x7C 1.485
0x1D 1.01 0x3D 1.17 0x5D 1.33 0x7D 1.49
0x1E 1.015 0x3E 1.175 0x5E 1.335 0x7E 1.495
0x1F 1.02 0x3F 1.18 0x5F 1.34 0x7F 1.5