SNVS999 May   2014 LM10507

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Handling Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  General Electrical Characteristics
    6. 7.6  Buck 1 Electrical Characteristics
    7. 7.7  Buck 2 Electrical Characteristics
    8. 7.8  Buck 3 Electrical Characteristics
    9. 7.9  LDO Electrical Characteristics
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Buck Regulators Operation
      2. 8.3.2 Buck Regulators Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 PWM Operation
      2. 8.4.2 PFM Operation (Bucks 1, 2 & 3)
      3. 8.4.3 Soft Start
      4. 8.4.4 Current Limiting
      5. 8.4.5 Internal Synchronous Rectification
      6. 8.4.6 Low Dropout Operation
      7. 8.4.7 Device Operating Modes
        1. 8.4.7.1  Startup Sequence
        2. 8.4.7.2  Power-On Default and Device Enable
        3. 8.4.7.3  RESET: Pin Function
        4. 8.4.7.4  DEVSLP (Device Sleep) Function
        5. 8.4.7.5  DEVSLP Terminal
        6. 8.4.7.6  Device Sleep (DEVSLP) Programming via SPI
        7. 8.4.7.7  ENABLE, Function
        8. 8.4.7.8  Under Voltage Lock Out (UVLO)
        9. 8.4.7.9  Over Voltage Lock Out (OVLO)
        10. 8.4.7.10 PWR_OK - Pin Function
        11. 8.4.7.11 Thermal Shutdown (TSD)
    5. 8.5 Programming
      1. 8.5.1 SPI Data Interface
    6. 8.6 Register Maps
      1. 8.6.1 Registers Configurable Via The SPI Interface
        1. 8.6.1.1 ADDR 0x07 & 0x08: Buck 1 and Buck 2 Voltage Code and VOUT Level Mapping
        2. 8.6.1.2 ADDR 0x00 Buck 3 Voltage Code and VOUT Level Mapping
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Input Voltage
        2. 9.2.2.2  Output Enable
        3. 9.2.2.3  Recommendations for Unused Functions and Pins
        4. 9.2.2.4  External Components Selection
        5. 9.2.2.5  Output Inductors and Capacitors Selection
        6. 9.2.2.6  Inductor Selection
        7. 9.2.2.7  Recommended Method for Inductor Selection
        8. 9.2.2.8  Alternate Method for Inductor Selection
        9. 9.2.2.9  Suggested Inductors and Their Suppliers
        10. 9.2.2.10 Output and Input Capacitors Characteristics
        11. 9.2.2.11 Output Capacitor Selection
        12. 9.2.2.12 Input Capacitor Selection
      3. 9.2.3 Application Performance Plots
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Layout Thermal Dissipation for DSBGA Package
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

34 bump DSBGA with 0.4mm pitch
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Pin Functions

Pin I/O Description
Name No.
VIN_B1 A/B5 I Buck Switcher Regulator 1 - Power supply voltage input for power stage PFET, if buck 1 is not used, tie to ground to reduce leakage.
SW_B1 A/B6 O Buck Switcher Regulator 1 - Power Switching node, connect to inductor
FB_B1 A/B4 I Buck Switcher Regulator 1 - Voltage output feedback for Buck Regulator 1
GND_B1 A/B7 G Buck Switcher Regulator 1 - Power ground for Buck Regulator
VIN_B2 G3 I Buck Switcher Regulator 2 - Power supply voltage input for power stage PFET, if buck 2 is not used, tie to ground to reduce leakage.
SW_B2 F/G2 O Buck Switcher Regulator 2 - Power Switching node, connect to inductor
FB_B2 F3 I Buck Switcher Regulator 2 - Voltage output feedback for Buck Regulator 2
GND_B2 G1 G Buck Switcher Regulator 2 - Power ground for Buck Regulator
VIN_B3 G5 I Buck Switcher Regulator 3 - Power supply voltage input for power stage PFET
SW_B3 F/G6 O Buck Switcher Regulator 3 - Power Switching node, connect to inductor
FB_B3 F5 I Buck Switcher Regulator 3 - Voltage output feedback for Buck Regulator 3
GND_B3 G7 G Buck Switcher Regulator 3 - Power ground for Buck Regulator
VIN A3 I Power supply Input Voltage, must be present for device to work
LDO A2 O LDO Regulator - LDO regulator output voltage
SPI_CS F1 I SPI Interface – chip select
SPI_DI D1 I SPI Interface – serial data input
SPI_DO E1 O SPI Interface – serial data output
SPI_CLK C1 I SPI Interface – serial clock input
ENABLE G4 I Digital Input Control Signal to Enable/Disable PMIC. Signal Level is related to VIN_IO. This is an active High pin with an internal pull-down resistor.
GND F4 I Digital Input Control Signal – Not Used – Connect to GND.
DEVSLP E7 I Digital Input Control Signal for entering Device Sleep Mode – see table 1. This is an active High pin with an internal pull-down resistor.
RESET F7 I Digital Input Control Signal to abort SPI transactions and resets the PMIC to default Voltages. This is an active Low pin with an internal pull-up resistor.
GND C7 I Not Used – Connect to GND.
PWR_OK A1 O Digital Output of Power Good signal – all output rails are started.
VIN_IO B1 P Supply Voltage for Digital Interface Signals to ASIC like SPI, RESET, DEVSLP, ENABLE, PWR_OK.
GND B2 G Ground. Connect to system Ground.
GND B3 G Ground. Connect to system Ground.
GND D7 G Ground. Connect to system Ground.
A: Analog Pin D : Digital Pin G: Ground Pin P: Power Pin I: Input Pin O: Output Pin