SNVSC12 April   2021 LM117QML-SP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configurations and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: 0.5–A IOUT Devices (LM117H, LM117GW)
    6. 7.6  Parameter Drift: 0.5–A IOUT Devices (LM117H, LM117GW)
    7. 7.7  Electrical Characteristics: 1.5–A IOUT Devices (LM117K)
    8. 7.8  Parameter Drift: 1.5–A IOUT Devices (LM117K)
    9. 7.9  Quality Conformance Inspection
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Setting Output Voltage
    4. 8.4 External Capacitors
    5. 8.5 Load Regulation
    6. 8.6 Protection Diodes
  9. 9 Application and Implementation
    1. 9.1 Typical Applications
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • K|2
  • NAC|16
  • Y|0
  • NDT|3
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configurations and Functions

GUID-B3F578E7-E10C-4A82-A583-D30B82643BE5-low.pngFigure 6-1 LM117K K Package
2-Pin TO-3 (Metal Can)
Bottom View
GUID-64BE2658-BEE7-4C7F-A3C5-CAB1E8B57B73-low.gifFigure 6-3 LM117GW NAC Package
16-Pin CFP SOIC
Top View
GUID-F84AEF32-618E-48DC-8B66-BD23F233970E-low.pngFigure 6-2 LM117H, LM117NDT NDT Package
3-Pin TO-39 (Metal Can)
Bottom View
Table 6-1 Pin Functions
PIN I/O DESCRIPTION
NAME TO-3 TO-39 CFP SOIC
ADJ 1 2 3 — Adjust pin
VIN 2 1 5 I Input voltage pin for the regulator
VOUT CASE 3, CASE 12 O Output voltage pin for the regulator
OUTPUT/SENSE — — 13 — Used to sense the output voltage. Must be connected to VOUT for proper operation.
N/C — — 1, 2, 4, 6, 7, 8, 9, 10, 11, 14, 15, 16 — No connection. These pins have no internal connections and may be grounded or left floating. They may also be connected to the board heatsink and used for thermal dissipation.