SNVS446D June   2006  – January 2016 LM1771

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Timing Opinion
      2. 7.3.2 Short-Circuit Protection
      3. 7.3.3 Precision Enable
      4. 7.3.4 Soft-Start
      5. 7.3.5 Jitter
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 LM1771 Typical Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Design Guide
            1. 8.2.1.2.1.1 Frequency Selection
            2. 8.2.1.2.1.2 Inductor Selection
            3. 8.2.1.2.1.3 Output Capacitor
            4. 8.2.1.2.1.4 Feedforward Capacitor
            5. 8.2.1.2.1.5 Input Capacitor
          2. 8.2.1.2.2 MOSFET Selection
            1. 8.2.1.2.2.1 VDS Voltage Rating
            2. 8.2.1.2.2.2 RDSON
            3. 8.2.1.2.2.3 Gate Drive
            4. 8.2.1.2.2.4 Gate Charge
            5. 8.2.1.2.2.5 Rise and Fall Times
            6. 8.2.1.2.2.6 Gate Charge Ratio
            7. 8.2.1.2.2.7 Feedback Resistors
          3. 8.2.1.2.3 Efficiency Calculations
            1. 8.2.1.2.3.1 Quiescent Current
            2. 8.2.1.2.3.2 Conduction Loss
            3. 8.2.1.2.3.3 Switching Loss
            4. 8.2.1.2.3.4 Transitional Loss
            5. 8.2.1.2.3.5 DCR Loss
            6. 8.2.1.2.3.6 Efficiency
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Example Application 5 VIN to 1.8 VOUT
      3. 8.2.3 Example Application 5 VIN to 3.3 VOUT
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The LM1771 synchronous buck controller has a control scheme that is referred to as adaptive ON-time control. This topology relies on a fixed switch ON-time to regulate the output voltage. This ON-time is internally set by EEPROM and is available with three different set-points to allow for different frequency options. The LM1771 automatically adjusts the ON-time during operation inversely with the input voltage (VIN) to maintain a constant frequency. Therefore the switching frequency during continuous conduction mode is independent of the inductor and capacitor size unlike hysteretic switchers.

At the beginning of the cycle, the LM1771 turns on the high-side PFET for a fixed duration. This ON-time is predetermined (internally set by EEPROM and adjusted by VIN) and the switch does not turn off until the timer has completed its period. The PFET then turns off for a minimum predetermined time period. This minimum TOFF of 150 ns is internally set and cannot be adjusted. This is to prevent false triggering from occurring on the comparator due to noise from the SW node transition. After the minimum TOFF period has expired, the PFET remains off until the comparator trip-point has been reached. Upon passing this trip-point (set at 0.8 V at the feedback pin), the PFET turns back on and the process repeats, thus regulating the output.

The NFET control is complementary to the PFET control with the exception of a short dead-time to prevent shoot-through from occurring.

7.2 Functional Block Diagram

LM1771 20189019.gif

7.3 Feature Description

7.3.1 Timing Opinion

Three versions of the LM1771 are available each with a predetermined TON set internally by EEPROM. This TON setting determines the switching frequency for the application. Derivation and calculation of the dependence of the switching frequency on VIN and TON is shown in Equation 1 through Equation 6.

In a PWM buck switcher, Equation 1, Equation 2, and Equation 3 can be manipulated to obtain the switching frequency. Equation 1 shows the standard duty-cycle equation given by the volts-seconds balance on the inductor with Equation 2 and Equation 3 defining standard relationships:

Equation 1. LM1771 20189020.gif
Equation 2. TON = D x TP
Equation 3. LM1771 20189021.gif

Using these equations and solving for duty-cycle for Equation 4:

Equation 4. D = fSW x TON

Frequency can now be expressed in Equation 5:

Equation 5. LM1771 20189022.gif

Or simply written as Equation 6:

Equation 6. LM1771 20189023.gif

where

  • α = VIN x TON

To maintain a set frequency in an application, α is always held constant by varying TON inversely with VIN. The three versions of the LM1771 are identified by the ON-times at a VIN of 3.3 V for consistency. For clarification, see Table 1.

Table 1. Timing for All Variants

Product ID TON at 3.3 V α (V µs)
LM1771S 0.5 µs 1.65
LM1771T 1.0 µs 3.3
LM1771U 2.0 µs 6.6

The variation of TON versus VIN can also be expressed graphically. These graphs can be found in the Typical Characteristics of the data sheet.

With α being a constant regardless of the version of the LM1771 used, Equation 6 shows that the only dependent variable remaining is VOUT. Because VOUT is a constant in any application, the frequency also remains constant. The switching frequency at which the application runs depends upon the VOUT desired and the LM1771 version chosen. For any VOUT, three frequency options (LM1771 versions) can be selected. This can be seen Table 2. The recommended frequency range of operation is 100 kHz to 1000 kHz.

Table 2. Frequency vs VOUT for Variants

VOUT TIMING OPTIONS (1)
500 ns 1000 ns 2000 ns
0.8 485 242 121
1 606 303 152
1.2 727 364 182
1.5 909 455 227
1.8 1091 545 273
2.5 1515 758 379
3.3 2000 1000 500
(1) Switching Frequency (kHz) of LM1771 based on output voltage and timing option.

7.3.2 Short-Circuit Protection

The LM1771 has an internal short-circuit comparator that constantly monitors the feedback node (except during soft-start). If the feedback voltage drops below 0.55 V (equivalent to the output voltage dropping below 68% of nominal), the comparator trips causing the part to latch off. The LM1771 does not resume switching until the input voltage is taken below the UVLO threshold and then brought back into its normal operating range, or the part is disabled then re-enabled through the enable pin. The purpose of this function is to prevent a severe short circuit from causing damage to the application. Due to the fast transient response of the LM1771 a severe short on the output causing the feedback to drop would only occur if the load applied had an effective resistance that approaches the PMOS RDS(ON).

7.3.3 Precision Enable

The LM1771 features a precision enable circuit. If the voltage on the EN pin is 1.2 V or greater, the part is enabled and switching occurs. If the enable voltage falls below 1.2 V, the part is placed into a shutdown state and the drivers is tri-stated. This allows the LM1771 to be easily sequenced using a resistive divider from the output of another regulator, or the working input voltage range of the LM1771 to be set using a resistive divider on VIN. There is no internal pullup connected to the EN pin, so an external signal is required to initiate switching.

NOTE

When power is first applied to the LM1771, there is a slight delay before the enable comparator is functional. During this delay, typically on the order of 400 µs, the part is disabled regardless of the voltage on the EN pin. The falling enable threshold features 50 mV of hysteresis

7.3.4 Soft-Start

To limit in-rush current and allow for a controlled start-up the LM1771 incorporates an internal soft-start scheme. Every time the enable voltage rises above 1.2 V while VIN is greater than the UVLO threshold, the LM1771 goes through an adaptive soft-start that limits the ON-time and expands the minimum OFF-time. In addition the part only activates the PMOS allowing a discontinuous mode of operation enabling a prebiased start-up. The time spent in soft-start depends on the load applied to the output, but is usually close to a set time that is dependent on the timing option. The approximate soft-start time can be seen in Table 3 for each timing option.

Table 3. Soft-Start Timing for All Variants

PRODUCT ID TIMING TSS
LM1771S 0.5 µs 1 ms
LM1771T 1.0 µs 1.2 ms
LM1771U 2.0 µs 1.8 ms

Therefore, if the input supply is extremely slow rising such that at the end of soft-start the input voltage is still near the UVLO threshold, a timing option must be chosen to ensure that maximum duty-cycle permits the output to meet the minimum condition. TI recommends using the 2000-ns option (LM1771U) in conditions where the output voltage is 2.5 V or greater to avoid false latch-offs when there is concern regarding the input supply slew rate.

NOTE

As soon as soft-start terminates the short-circuit protection is enabled. This means that if the output voltage does not reach at least 68% of its final value the part latches off.

In some situations, the internal soft-start routine can create a slight overshoot on the output voltage. If this must be avoided, the use of a feedforward capacitor as detailed in the Feedforward Capacitor section.

7.3.5 Jitter

The LM1771 uses an adaptive ON-time control scheme that relies on the output voltage ripple to provide a consistent switching frequency. Under certain conditions, excessive noise can couple onto the feedback pin causing the switch node to appear to have a slight amount of jitter. This is not indicative of an unstable design. The output voltage still regulates to the exact same value. Careful component selection and layout must minimize any external influence.

In addition to any external noise that can add to the jitter seen on the switch node, the LM1771 always has a slight amount of switch jitter. This is because the LM1771 makes a small alteration in the reference voltage every 128 cycles to improve its accuracy and long-term performance. This has the effect of causing a change in the switching frequency at that instant. When viewed on an oscilloscope this can be seen as a jitter in the switch node. The change in feedback voltage or output voltage, however, is almost indistinguishable.

7.4 Device Functional Modes

The LM1771 has essentially one normal operational mode: in normal operation, the part operates in full synchronous mode to regulate the FB input to 0.8 V (typical) after soft-start period is over. The EN pin allows the user to shut down the part. When the part is enabled, the IC enters soft-start for 1 ms to 1.8 ms depending on the variant of the IC. See Soft-Start for more detail on the soft-start pattern.