SNVSCB6B February   2023  – September 2023 LM2005

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Start-Up and UVLO
      2. 7.3.2 Input Stages
      3. 7.3.3 Level Shift
      4. 7.3.4 Output Stages
      5. 7.3.5 SH Transient Voltages Below Ground
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select Bootstrap and GVDD Capacitor
        2. 8.2.2.2 Select External Gate Driver Resistor
        3. 8.2.2.3 Estimate the Driver Power Loss
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Switching Characteristics

VGVDD = VBST = 12 V, GND = VSH = 0 V, No Load on GL or GH, TJ = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PROPAGATION DELAYS
tDLFF VINL falling to VGL falling VINH = VINL = 0-3 V, CLOAD = 0 pF. Time from 50% of the input to 90% of the output. 115 ns
tDHFF VINH falling to VGH falling VINH = VIN L= 0-3 V, CLOAD = 0 pF. Time from 50% of the input to 90% of the output. 115 ns
tDLRR VINL rising to VGL rising VINH = VINL = 0-3 V, CLOAD = 0 pF. Time from 50% of the input to 10% of the output. 115 ns
tDHRR VINH rising to VGH rising VINH = VINL = 0-3 V, CLOAD = 0 pF. Time from 50% of the input to 10% of the output. 115 ns
DELAY MATCHING
tMON Delay from GL on to GH off INL ON, INH OFF, VINH = VINL = 0-3 V 30 ns
tMOFF Delay from GL off to GH on INL OFF, INH ON, VINH = VINL = 0-3 V 30 ns
OUTPUT RISE AND FALL TIME
tR_GL GL CLOAD = 1000 pF, VINH = VINL = 0-3 V 28 ns
tR_GH GH CLOAD = 1000 pF, VINH = VINL = 0-3 V 28 ns
tF_GL GL CLOAD = 1000 pF, VINH = VINL = 0-3 V 18 ns
tF_GH GH CLOAD = 1000 pF, VINH = VINL = 0-3 V 18 ns