Table 1. Design Parameters

Table 2. Bill of Materials

8.2.1.2.1 Duty Cycle Calculation

The first equation to calculate for any buck converter is duty-cycle. Ignoring conduction losses associated with the FETs and parasitic resistances it can be approximated with Equation 3.

Equation 3.

The example design the typical duty cycle is calculated to be 66%.

8.2.1.2.2 Inductor Selection (L)

The inductor value is determined based on the operating frequency, load current, ripple current, and duty cycle.  To optimize the performance and prevent the device from entering current limit at maximum load, the inductance is typically selected such that the ripple current, ΔiL, is between 25% and 50% of the rated output current. In general, the inductor ripple current, Δi_L, should be greater than 10% of the rated output current to provide adequate current sense information for the current mode control loop. Figure 33 illustrates the switch and inductor ripple current waveforms. Once the input voltage, output voltage, operating frequency, and desired ripple current are known, the minimum value for the inductor can be calculated with Equation 4.

Equation 4.

For the example design the calculated inductance is between .405 μH and 0.810 μH.

The inductor selected should have a saturation current rating greater than the peak current limit of the device listed in the Electrical Characteristics table. Keep in mind the specified current limit does not account for delay of the current limit comparator, therefore the current limit in the application may be higher than the specified value. Peak current can be calculated using Equation 5. This value needs to be less than the part current limit threshold. If needed, slightly smaller value inductors can be used, however, the peak inductor current should be kept below the peak current limit of the device.

Equation 5.

For the example design the peak inductor current is between 4.563 A and 6.125 A for the selected inductor ripple current range.

Due to exceeding current limit and adding flexibility to accommodate the entire output voltage range a inductance of 1.2 μH was selected, resulting in a peak inductor current of 4.056 A.

Figure 33. Switch and Inductor Current Waveforms

8.2.1.2.3 Output Capacitor Selection (C_OUT)

The output capacitor, C_OUT, filters the inductor ripple current and provides a source of charge for transient load conditions. A wide range of output capacitors may be used with the LM20143 that provide excellent performance. The best performance is typically obtained using ceramic, SP, or OSCON type chemistries. Typical trade-offs are that the ceramic capacitor provides extremely low ESR to reduce the output ripple voltage and noise spikes, while the SP and OSCON capacitors provide a large bulk capacitance in a small volume for transient loading conditions.

When selecting the value for the output capacitor the two performance characteristics to consider are the output voltage ripple and transient response. The output voltage ripple can be approximated by using Equation 6.

Equation 6.

where

• ΔV_OUT (V) is the amount of peak to peak voltage ripple at the power supply output
• R_ESR (Ω) is the series resistance of the output capacitor
• f_SW(Hz) is the switching frequency
• C_OUT (F) is the output capacitance used in the design

The amount of output ripple that can be tolerated is application specific; however a general recommendation is to keep the output ripple less than 1% of the rated output voltage. Keep in mind ceramic capacitors are sometimes preferred because they have very low ESR; however, depending on package and voltage rating of the capacitor the value of the capacitance can drop significantly with applied voltage. The output capacitor selection will also affect the output voltage droop during a load transient. The peak droop on the output voltage during a load transient is dependent on many factors; however, an approximation of the transient droop ignoring loop bandwidth can be obtained using Equation 7. Both the tolerance and voltage coefficient of the capacitor needs to be examined when designing for a specific output ripple or transient drop target.

Equation 7.

where

• C_OUT (F) is the minimum required output capacitance
• L (H) is the value of the inductor
• V_DROOP (V) is the output voltage drop ignoring loop bandwidth considerations
• ΔI_OUTSTEP (A) is the load step change
• R_ESR (Ω) is the output capacitor ESR
• V_IN (V) is the input voltage
• V_OUT (V) is the set regulator output voltage

For the example design, a 47-µF ceramic capacitor is selected for the output capacitor to provide good transient and DC performance in a relatively small package. From the technical specifications of this capacitor, the ESR is roughly 3 mΩ, and the effective in-circuit capacitance is approximately 32 µF (reduced from 47 µF due to the 1.2 V DC bias). With these values, the peak-to-peak voltage ripple on the output when operating from a 5-V input can be calculated to be 3 mV.  A load transient from 1.5 A to 3 A is calculated to create a 27-mV droop.

8.2.1.2.4 Input Capacitor Selection (C_IN)

Good quality input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current during the on-time. In general it is recommended to use a ceramic capacitor for the input as they provide both a low impedance and small footprint. One important note is to use a good dielectric for the ceramic capacitor such as X5R or X7R. These provide better over temperature performance and also minimize the DC voltage derating that occurs on Y5V capacitors. For most applications, a 22-µF, X5R, 6.3-V input capacitor is sufficient; however, additional capacitance may be required if the connection to the input supply is far from the PVIN pins. The input capacitor should be placed as close as possible PVIN and PGND pins of the device.

Non-ceramic input capacitors should be selected for RMS current rating and minimum ripple voltage. A good approximation for the required ripple current rating is given by Equation 8.

Equation 8.

As indicated by the RMS ripple current equation, highest requirement for RMS current rating occurs at 50% duty cycle. For this case, the RMS ripple current rating of the input capacitor should be greater than half the output current. For best performance, low ESR ceramic capacitors should be placed in parallel with higher capacitance capacitors to provide the best input filtering for the device.

For the example design the rated RMS current must be at least 1.5 A. A 47-µF ceramic capacitor  provides the necessary input capacitance for the evaluation board. For improved bypassing, a small 1-µF high frequency capacitor is placed in parallel with the 47-µF bulk capacitor to filter high frequency noise pulses on the supply.

8.2.1.2.5 Setting the Output Voltage (R_FB1, R_FB2)

The resistors R_FB1 and R_FB2 are selected to set the output voltage for the device. For most applications, R_FB1 should be between 4.99 kΩ to 49.9 kΩ.

Equation 9.

For the example design R_FB1 = 4 kΩ and R_FB2 = 10 kΩ to set the output voltage at 1.2 V.

Table 3 contains common output voltage values for R_FB1 and R_FB2.

8.2.1.2.6 Adjusting the Operating Frequency (R_T)

The LM20143 supports a wide range of switching frequencies from 500 kHz to 1.5 MHz. The operating frequency of the LM20143 can be adjusted by connecting a resistor from the RT pin to ground. The choice of switching frequency is usually a compromise between efficiency and the size of the circuit. Lower switching frequency implies reduced switching losses, usually resulting in higher overall efficiency. However, higher switching frequency allows use of smaller inductor and  output capacitor components, resulting in a smaller design. The optimal switching frequency is usually a tradeoff in a given application and thus should be determined on a case-by-case basis. For the design example a relatively high switching frequency was selected to minimize circuit size. Equation 10 can be used to calculate the value of R_T for a given operating frequency.

Equation 10.

where

• f_SW is the switching frequency in kHz
• R_T is the frequency adjust resistor in kΩ

Please refer to the curve Oscillator Frequency verses R_T in the typical performance characteristics section. If the R_T resistor is omitted the device will not operate.

For the example design RT was calculated to be 49.9 kΩ to give a switching frequency of 1.5 MHz.

8.2.1.2.7 AVIN Filtering Components (C_F and R_F)

To prevent high frequency noise spikes from disturbing the sensitive analog circuitry connected to the AVIN and AGND pins, a high frequency RC filter is required between PVIN and AVIN. These components are shown in Figure 32 as C_F and R_F. The required value for R_F is 1 Ω. C_F must be used. Recommended value of C_F is 1.0 µF. The filter capacitor, C_F should be placed as close to the IC as possible with a direct connection from AVIN to AGND. A good quality X5R or X7R ceramic capacitor should be used for C_F.

For the example design, R_F 1 Ω and C_F is 1.0 µF, providing greater than 16 dB of attenuation at the set 1.5-MHz switching frequency.

8.2.1.2.8 Sub-Regulator Bypass Capacitor (C_VCC)

The capacitor at the VCC pin provides noise filtering and stability for the internal sub-regulator. The recommended value of C_VCC should be no smaller than 1 µF and no greater than 10 µF. The capacitor should be a good quality ceramic X5R or X7R capacitor. In general, a 1-µF ceramic capacitor is recommended for most applications. In the example design, C_VCC is 1 µF.

8.2.1.2.9 Setting the Start Up Time (C_SS)

The addition of a capacitor connected from the SS pin to ground sets the time at which the output voltage will reach the final regulated value. Larger values for CSS will result in longer start up times. While the Soft-Start capacitor can be sized to meet many start up requirements, there are limitations to its size. The Soft-Start time can never be faster than 1 ms due to the internal default 1-ms start up time. When the device is enabled there is an approximate time interval of 50 μs when the Soft-Start capacitor will be discharged just prior to the Soft-Start ramp. If the enable pin is rapidly pulsed or the Soft-Start capacitor is large there may not be enough time for CSS to completely discharge resulting in start up times less than predicted. To aid in discharging of Soft-Start capacitor during long disable periods an external 1-MΩ resistor from SS/TRK to ground can be used without greatly affecting the start up time. Equation 11 can be used to calculate the desired soft start time. For the LM20143, I_SS is nominally 5 µA, that may be found in the electrical characteristics table.

Equation 11.

For the example design the start-up time was set to be around 5ms resulting in a 33 nF capacitor.

Table 4 shows values of C_SS for some common start up times.

8.2.1.2.10 Loop Compensation (R_C1, C_C1)

The purpose of loop compensation is to meet static and dynamic performance requirements while maintaining adequate stability. Optimal loop compensation depends on the output capacitor, inductor, load, and the device itself. Table 5 gives values for the compensation network that will result in a stable system when using a 100-µF, 6.3-V ceramic X5R output capacitor and 1-µH inductor.

If the desired solution differs from those provided, the loop transfer function should be analyzed to optimize the loop compensation. The overall loop transfer function is the product of the power stage and the feedback network transfer functions. For stability purposes, the objective is to have a loop gain slope that is –20 db/decade from a very low frequency to beyond the crossover frequency. Figure 34 shows the transfer functions for power stage, feedback/compensation network, and the resulting closed loop system for the LM20143.

Figure 34. LM20143 Loop Compensation

The power stage transfer function is dictated by the modulator, output LC filter, and load; while the feedback transfer function is set by the feedback resistor ratio, error amp gain, and external compensation network.

To achieve a –20 dB/decade slope, the error amplifier zero, located at f_Z(EA), should positioned to cancel the output filter pole (f_P(FIL)). An additional error amp pole, located at f_P2(EA), can be added to cancel the output filter zero at f_Z(FIL). Cancellation of the output filter zero is recommended if larger value, non-ceramic output capacitors are used.

Compensation of the LM20143 is achieved by adding an RC network as shown in Figure 35.

Figure 35. Compensation Network for LM20143

A good starting value for C_C1 for most applications is 4.7 nF. Once the value of C_C1 is chosen the value of RC should be calculated using Equation 12 to cancel the output filter pole (f_P(FIL)) as shown in Figure 34.

Equation 12.

A higher crossover frequency can be obtained, usually at the expense of phase margin, by lowering the value of C_C1 and recalculating the value of R_C1. Likewise, increasing C_C1 and recalculating R_C1 will provide additional phase margin at a lower crossover frequency. As with any attempt to compensate the LM20143 the stability of the system should be verified for desired transient droop and settling time.

If the output filter zero, f_Z(FIL) approaches the crossover frequency (F_C), an additional capacitor (C_C2) should be placed at the COMP pin to ground. This capacitor adds a pole to cancel the output filter zero assuring the crossover frequency will occur before the double pole at f_SW / 2 degrades the phase margin. The output filter zero is set by the output capacitor value and ESR as shown in Equation 13.

Equation 13.

If needed, the value for C_C2 should be calculated using Equation 14.

Equation 14.

where

• R_ESR is the output capacitor series resistance
• R_C1 is the calculated compensation resistance

For the example design R_C1 is 1 kΩ, C_C1 is 4.7 nF and C_C2is left open.

Table 6. Design Parameters

Table 7. Bill of Materials

Table 8. Design Parameters

Table 9. Bill of Materials