7.3.1 Peak Current Mode Control

In most cases, the peak current mode control architecture used in the LM20143 only requires two external components to achieve a stable design. The compensation can be selected to accommodate any capacitor type or value. The external compensation also allows the user to set the crossover frequency and optimize the transient performance of the device.

For duty cycles above 50% all current mode control buck converters require the addition of an artificial ramp to avoid sub-harmonic oscillation. This artificial linear ramp is commonly referred to as slope compensation. What makes the LM20143 unique is the amount of slope compensation will change depending on the output voltage. When operating at high output voltages the device will have more slope compensation than when operating at lower output voltages. This is accomplished in the LM20143 by using a non-linear parabolic ramp for the slope compensation. The parabolic slope compensation of the LM20143 is much better than the traditional linear slope compensation because it optimizes the stability of the device over the entire output voltage range.

7.3.2 Precision Enable

The enable (EN) pin allows the output of the device to be enabled or disabled with an external control signal. This pin is a precision analog input that enables the device when the voltage exceeds 1.2 V (typical). The EN pin has 100 mV of hysteresis and will disable the output when the enable voltage falls below 1.1 V (typical). If the EN pin is not used, it should be connected to VIN. Since the enable pin has a precise turn-on threshold it can be used along with an external resistor divider network from V_IN to configure the device to turn-on at a precise input voltage. The precision enable circuitry will remain active even when the device is disabled.

7.3.3 Current Limit

The precise current limit of the LM20143 is set at the factory to be within 10% over the entire operating temperature range. This enables the device to operate with smaller inductors that have lower saturation currents. When the peak inductor current reaches the current limit threshold, an over current event is triggered and the internal high-side FET turns off and the low-side FET turns on allowing the inductor current to ramp down until the next switching cycle. For each sequential over-current event, the reference voltage is decremented and PWM pulses are skipped resulting in a current limit that does not aggressively fold back for brief over-current events, while at the same time providing frequency and voltage foldback protection during hard short circuit conditions.

7.3.4 Pre-Bias Start Up Capability

The LM20143 is in a pre-biased state when the device starts up with an output voltage greater than zero. This often occurs in many multi-rail applications such as when powering an FPGA, ASIC, or DSP. In these applications the output can be pre-biased through parasitic conduction paths from one supply rail to another. Even though the LM20143 is a synchronous converter it will not pull the output low when a pre-bias condition exists. During start up the LM20143 will not sink current until the Soft-Start voltage exceeds the voltage on the FB pin. Since the device can not sink current it protects the load from damage that might otherwise occur if current is conducted through the parasitic paths of the load.

7.3.5 Soft-Start and Voltage Tracking

The SS/TRK pin is a dual function pin that can be used to set the start up time or track an external voltage source. The start up or Soft-Start time can be adjusted by connecting a capacitor from the SS/TRK pin to ground. The Soft-Start feature allows the regulator output to gradually reach the steady state operating point, thus reducing stresses on the input supply and controlling start up current. If no Soft-Start capacitor is used the device defaults to the internal Soft-Start circuitry resulting in a start up time of approximately 1 ms. For applications that require a monotonic start up or utilize the PGOOD pin, an external Soft-Start capacitor is recommended. The SS/TRK pin can also be set to track an external voltage source. The tracking behavior can be adjusted by two external resistors connected to the SS/TRK pin as shown in Figure 29.

7.3.6 Power Good and Overvoltage Fault Handling

The LM20143 has built in under and over voltage comparators that control the power switches. Whenever there is an excursion in output voltage above the set OVP threshold, the part will terminate the present on-pulse, turn-on the low-side FET, and pull the PGOOD pin low. The low-side FET will remain on until either the FB voltage falls back into regulation or the zero cross detection is triggered which in turn tri-states the FETs. If the output reaches the UVP threshold the part will continue switching and the PGOOD pin will be asserted and go low. Typical values for the PGOOD resistor are on the order of 100 kΩ or less. To avoid false tripping during transient glitches the PGOOD pin has 16 µs of built in deglitch time to both rising and falling edges.

7.3.7 UVLO

The LM20143 has a built-in under-voltage lockout protection circuit that keeps the device from switching until the input voltage reaches 2.7 V (typical). The UVLO threshold has 45 mV of hysteresis that keeps the device from responding to power-on glitches during start up. If desired the turn-on point of the supply can be changed by using the precision enable pin and a resistor divider network connected to V_IN as shown in Figure 31. in the design guide.

7.3.8 Thermal Protection

Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. When activated, typically at 160°C, the LM20143 tri-states the power FETs and resets soft start. After the junction cools to approximately 150°C, the part starts up using the normal start up routine. This feature is provided to prevent catastrophic failures from accidental device overheating.

7.4.1 Light Load Operation

The LM20143 offers increased efficiency when operating at light loads. Whenever the load current is reduced to a point where the peak to peak inductor ripple current is greater than two times the load current, the part will enter the diode emulation mode preventing significant negative inductor current. The point at which this occurs is the critical conduction boundary and can be calculated by Equation 1

Equation 1.

Several diagrams are shown in Figure 28 illustrating continuous conduction mode (CCM), discontinuous conduction mode, and the boundary condition.

It can be seen that in diode emulation mode, whenever the inductor current reaches zero the SW node will become high impedance. Ringing will occur on this pin as a result of the LC tank circuit formed by the inductor and the parasitic capacitance at the node. If this ringing is of concern an additional RC snubber circuit can be added from the switch node to ground.

At very light loads, usually below 100 mA, several pulses may be skipped in between switching cycles, effectively reducing the switching frequency and further improving light-load efficiency.

Figure 28. Modes of Operation for LM20143

7.4.2 Tracking an External Supply

By using a properly chosen resistor divider network connected to the SS/TRK pin, as shown in Figure 29, the output of the LM20143 can be configured to track an external voltage source to obtain a simultaneous or ratiometric start up.

Figure 29. Tracking an External Supply

Since the Soft-Start charging current I_SS is always present on the SS/TRK pin, the size of R2 should be less than 10 kΩ to minimize the errors in the tracking output. Once a value for R2 is selected the value for R1 can be calculated using appropriate equation in Figure 30, to give the desired start up. Figure 30 shows two common start up sequences; the top waveform shows a simultaneous start up while the waveform at the bottom illustrates a ratiometric start up.

Figure 30. Common Start Up Sequences

A simultaneous start up is preferred when powering most FPGAs, DSPs, or other microprocessors. In these systems the higher voltage, V_OUT1, usually powers the I/O, and the lower voltage, V_OUT2, powers the core. A simultaneous start up provides a more robust power up for these applications since it avoids turning on any parasitic conduction paths that may exist between the core and the I/O pins of the processor.

The second most common power on behavior is known as a ratiometric start up. This start up is preferred in applications where both supplies need to be at the final value at the same time.

Similar to the Soft-Start function, the fastest start up possible is 1ms regardless of the rise time of the tracking voltage. When using the track feature the final voltage seen by the SS/TRACK pin should exceed 1V to provide sufficient overdrive and transient immunity.

7.4.3 Using Precision Enable and Power Good

The precision enable (EN) and power good (PGOOD) pins of the LM20143 can be used to address many sequencing requirements. The turn-on of the LM20143 can be controlled with the precision enable pin by using two external resistors as shown in Figure 31.

Figure 31. Sequencing LM20143 with Precision Enable

The value for resistor R_B can be selected by the user to control the current through the divider. Typically this resistor will be selected to be between 10 kΩ and 1 MΩ. Once the value for R_B is chosen the resistor R_A can be solved using Equation 2 to set the desired turn-on voltage.

Equation 2.

When designing for a specific turn-on threshold (V_TO) the tolerance on the input supply, enable threshold (V_{IH_EN}), and external resistors needs to be considered to insure proper turn-on of the device.

The LM20143 features an open drain power good (PGOOD) pin to sequence external supplies or loads and to provide fault detection. This pin requires an external resistor (R_PG) to pull PGOOD high while when the output is within the PGOOD tolerance window. Typical values for this resistor range from 10 kΩ to 100 kΩ.