SNVSCH8A September   2023  – October 2023 LM2104

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Start-Up and UVLO
      2. 7.3.2 Input Stages
      3. 7.3.3 Level Shift
      4. 7.3.4 Output Stages
      5. 7.3.5 SH Transient Voltages Below Ground
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select Bootstrap and GVDD Capacitor
        2. 8.2.2.2 Select External Gate Driver Resistor
        3. 8.2.2.3 Estimate the Driver Power Loss
      3. 8.2.3 Application Curves
  10. Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Estimate the Driver Power Loss

The total driver IC power dissipation can be estimated through the following components.

  1. Static power losses, PQC, due to quiescent currents IGVDD and IBST is shown in Equation 11.
    Equation 11. PQC = VGVDD × IGVDD + (VGVDD – VF) × IBST = 12V × 0.43mA + (12V – 1V) × 0.15mA = 6.8mW
  2. Level-shifter losses, PIBSTS, due high-side leakage current IBSTS is shown in Equation 12.
    Equation 12. PIBSTS = VBST × IBSTS × D = 72V × 0.033mA × 0.95 = 2.26mW

    where

    • D is the high-side switch duty cycle
  3. Dynamic losses, PQG1&2, due to the FETs gate charge QG as shown in Equation 13.
    Equation 13. P Q G 1 & 2 = 2 × V G V D D × Q G × f S W × R G D _ R R G D _ R + R G A T E + R G F E T _ I N T =   2 × 12 V × 17 n C × 50 k H z × 5.25 5.25 + 4.7 + 2.2 = 8.8 m W

    where

    • QG = Total FETs gate charge
    • fSW = Switching frequency
    • RGD_R = Average value of pullup and pulldown resistor
    • RGATE = External gate drive resistor
    • RGFET_INT = Internal FETs gate resistor
  4. Level-shifter dynamic losses, PLS, during high-side switching due to required level-shifter charge on each switching cycle. For this example it is assumed that value of parasitic charge QP is 2.5 nC, as shown in Equation 14.
    Equation 14. PLS = VBST × QP × fSW = 72V × 2.5nC × 50kHz = 9mW

In this example, the sum of all the losses is 27 mW as a total gate driver loss. For gate drivers that include bootstrap diode, one should also estimate losses in the bootstrap diode. Diode forward conduction loss is computed as product of average forward voltage drop and average forward current.

Equation 15 estimates the maximum allowable power loss of the device for a given ambient temperature.

Equation 15. P M A X = T J - T A R θ J A

where

  • PMAX = Maximum allowed power dissipation in the gate driver device
  • TJ = Junction temperature
  • TA = Ambient temperature
  • RθJA = Junction-to-ambient thermal resistance

The thermal metrics for the driver package is summarized in the Thermal Information table of the data sheet. For detailed information regarding the thermal information table, refer to the Texas Instruments application note entitled Semiconductor and IC Package Thermal Metrics.