The total driver IC power dissipation can be estimated through the following components.

1. Static power losses, P_QC, due to quiescent currents I_GVDD and I_BST is shown in Equation 11.
   Equation 11. P_QC = V_GVDD × I_GVDD + (V_GVDD – V_F) × I_BST = 10V × 0.43mA + (10V – 0.6V) × 0.13mA = 5.52mW
2. Level-shifter losses, P_IBSTS, due high-side leakage current I_BSTS is shown in Equation 12.
   Equation 12. P_IBSTS = V_BST × I_BSTS × D = 72V × 0.033mA × 0.95 = 2.26mW

   where

   • D is the high-side switch duty cycle
3. Dynamic losses, P_QG1&2, due to the FETs gate charge Q_G as shown in Equation 13.
   Equation 13. ${\mathrm{P}}_{\mathrm{Q}\mathrm{G}1\&2}=2\times {\mathrm{V}}_{\mathrm{G}\mathrm{V}\mathrm{D}\mathrm{D}}\times {\mathrm{Q}}_{\mathrm{G}}\times {\mathrm{f}}_{\mathrm{S}\mathrm{W}}\times \frac{{\mathrm{R}}_{\mathrm{G}\mathrm{D}\_\mathrm{R}}}{{\mathrm{R}}_{\mathrm{G}\mathrm{D}\_\mathrm{R}}+{\mathrm{R}}_{\mathrm{G}\mathrm{A}\mathrm{T}\mathrm{E}}+{\mathrm{R}}_{\mathrm{G}\mathrm{F}\mathrm{E}\mathrm{T}\_\mathrm{I}\mathrm{N}\mathrm{T}}}=\mathrm{ }2\times 10\mathrm{V}\times 17\mathrm{n}\mathrm{C}\times 50\mathrm{k}\mathrm{H}\mathrm{z}\times \frac{5.25\mathrm{\Omega }}{5.25\mathrm{\Omega }+4.7\mathrm{\Omega }+2.2\mathrm{\Omega }}=7.35\mathrm{m}\mathrm{W}$

   where

   • Q_G = Total FETs gate charge
   • f_SW = Switching frequency
   • R_{GD_R} = Average value of pullup and pulldown resistor
   • R_GATE = External gate drive resistor
   • R_{GFET_INT} = Internal FETs gate resistor
4. Level-shifter dynamic losses, P_LS, during high-side switching due to required level-shifter charge on each switching cycle. For this example it is assumed that value of parasitic charge Q_P is 2.5 nC, as shown in Equation 14.
   Equation 14. P_LS = V_BST × Q_P × f_SW = 72V × 2.5nC × 50kHz = 9mW

In this example, the sum of all the losses is 24 mW as a total gate driver loss. For gate drivers that include bootstrap diode, one should also estimate losses in the bootstrap diode. Diode forward conduction loss is computed as product of average forward voltage drop and average forward current.

Equation 15 estimates the maximum allowable power loss of the device for a given ambient temperature.

where

• P_MAX = Maximum allowed power dissipation in the gate driver device
• T_J = Junction temperature
• T_A = Ambient temperature
• R_θJA = Junction-to-ambient thermal resistance

The thermal metrics for the driver package is summarized in the Thermal Information table of the data sheet. For detailed information regarding the thermal information table, refer to the Texas Instruments application note entitled Semiconductor and IC Package Thermal Metrics.