SNVS671F
February 2011 – May 2019
LM21212-1
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
Simplified Application Circuit
4
Revision History
5
Description
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Typical Performance Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Frequency Synchronization
8.3.2
Precision Enable
8.3.3
UVLO
8.3.4
Current Limit
8.3.5
Short-Circuit Protection
8.3.6
Thermal Protection
8.3.7
Power-Good Flag
8.3.8
Light Load Operation
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Detailed Design Procedure
9.2.1.1
Custom Design With WEBENCH® Tools
9.2.1.2
Output Voltage
9.2.1.3
Precision Enable
9.2.1.4
Soft Start
9.2.1.5
Inductor Selection
9.2.1.6
Output Capacitor Selection
9.2.1.7
Input Capacitor Selection
9.2.1.8
Control Loop Compensation
9.2.2
Application Curves
10
Layout
10.1
Pcb Layout Considerations
10.2
Thermal Considerations
11
Device and Documentation Support
11.1
Device Support
11.1.1
Third-Party Products Disclaimer
11.1.2
Development Support
11.1.2.1
Custom Design With Webench® Tools
11.2
Receiving Notification Of Documentation Updates
11.3
Community Resources
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Mechanical, Packaging, And Orderable Information
Package Options
Mechanical Data (Package|Pins)
PWP|20
MHTS001H
Thermal pad, mechanical data (Package|Pins)
PWP|20
PPTD299A
Orderable Information
snvs671f_oa
snvs671f_pm
7.6
Typical Performance Characteristics
Unless otherwise specified: V
VIN
= 5V, V
OUT
= 1.2V, L= 0.56µH (1.8mΩ R
DCR
), C
SS
= 33nF, f
SW
= 1 MHz, T
A
= 25°C for efficiency curves, loop gain plots and waveforms, and T
J
= 25°C for all others.
Figure 1.
Efficiency
V
OUT
= 2.5 V
f
SW
= 300 KHz
Inductor P/N Ser2010-102mld
Figure 3.
Efficiency
Figure 5.
Line Regulation
Figure 7.
Non-Switching I
AVIN
and I
PVIN
vs Temperature
Figure 9.
Enable Threshold and Hysteresis vs Temperature
Figure 11.
Enable Low Current vs Temperature
Figure 13.
Minimum On-Time vs Temperature
Figure 15.
Peak Current Limit vs Temperature
4 µs/DIV
Figure 17.
Sync Signal Acquired
200 µs/DIV
Figure 19.
Start-up With SS/TRK Open Circuit
100 µs/DIV
Figure 21.
Output Overcurrent Condition
Figure 2.
Efficiency
Figure 4.
Load Regulation
Figure 6.
Non-Switching I
QTOTAL
vs V
IN
Figure 8.
V
FB
vs Temperature
Figure 10.
UVLO Threshold and Hysteresis vs Temperature
Figure 12.
OVP/UVP Threshold vs Temperature
Figure 14.
FET Resistance vs Temperature
4 µs/DIV
Figure 16.
Sync Signal Lost
2 ms/DIV
Figure 18.
Start-up With Prebiased Output
200 ms/DIV
Figure 20.
Start-up With Applied Track Signal