SNOSB87D March   2011  – May 2019 LM21215A

PRODUCTION DATA.  

  1. Features
  2. Applications
    1.     Efficiency at 2.5 V, 500 kHz
  3. Description
    1.     Typical Application Circuit
      1.      Device Images
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Precision Enable
      2. 7.3.2 Input Voltage UVLO
      3. 7.3.3 Soft-Start Capability
      4. 7.3.4 PGOOD Indicator
      5. 7.3.5 Frequency Synchronization
      6. 7.3.6 Current Limit
      7. 7.3.7 Short Circuit Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Light-Load Operation
      2. 7.4.2 Overvoltage and Undervoltage Handling
      3. 7.4.3 Thermal Shutdown
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application 1
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2 Output Voltage Setpoint
          3. 8.2.1.2.3 Precision Enable
          4. 8.2.1.2.4 Filter Inductor Selection
          5. 8.2.1.2.5 Output Capacitor Selection
          6. 8.2.1.2.6 Input Capacitor Selection
          7. 8.2.1.2.7 Control Loop Compensation
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical Application 2
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Compact PCB Layout for EMI Reduction
      2. 10.1.2 Thermal Design
      3. 10.1.3 Ground Plane Design
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Control Loop Compensation

This section walks through the various steps in obtaining the open-loop transfer function. There are three main blocks of a voltage-mode buck converter that the power supply designer must consider when designing the control system: the power stage, the PWM modulator, and the compensated error amplifier. The control loop architecture of a voltage-mode buck converter is provided in Figure 32.

LM21215A Circuit3_nosb87.gifFigure 32. Voltage-mode Buck Converter Architecture

The power stage consists of the filter inductor (LF) with DCR (DC resistance RDCR), output capacitor (COUT) with ESR (effective series resistance RESR), and load resistance (RO). The LM21215A incorporates a high-bandwidth error amplifier between the FB and COMP pins to achieve high loop bandwidth. The error amplifier (EA) constantly regulates FB to 0.6 V. The compensation component network around the error amplifier establish system stability. The modulator creates the duty cycle command by comparing the error amplifier output with an internally-generated PWM ramp set at the switching frequency.

There are three transfer functions that are taken into consideration when obtaining the total open-loop transfer function; COMP-to-duty cycle (modulator), duty cycle-to-VOUT (power stage), and VOUT-to-COMP (compensator). If ΔVRAMP is the peak-to-peak ramp voltage (nominally 0.8 V), the COMP-to-duty cycle transfer function is simply the PWM modulator gain given by Equation 10.

Equation 10. LM21215A q_GPWM_nosb87.gif

The duty cycle-to-output transfer function includes the filter inductor, output capacitor, and output load resistance. The inductor and capacitor create a pair of complex poles at the LC tank frequency expressed by Equation 11.

Equation 11. LM21215A q_fLC_nosb87.gif

In addition to two complex poles, a left half plane zero is created by the output capacitor ESR located at a frequency described by Equation 12.

Equation 12. LM21215A q_F_ESR_nosb87.gif

A Bode plot showing the –40dB/decade power stage response is shown in Figure 33

LM21215A 30152140.gifFigure 33. Power Stage Bode Plot

The complex poles created by the filter inductor and output capacitor cause a 180° phase lag. The phase is boosted back up to –90° by the output capacitor ESR zero. The compensator must provide sufficient phase boost to stabilize the loop response. The type-III compensation network shown around the error amplifier in Figure 32 creates two poles, two zeros and a pole at the origin. Placing these poles and zeros at the correct frequencies stabilizes the closed loop response. The compensator transfer function is given by Equation 13.

Equation 13. LM21215A q_Gc_nosb87.gif

where

  • Kmid is the mid-band gain, RC1/RFB1

The pole located at the origin gives high open-loop gain at DC, translating into improved load regulation accuracy. This pole occurs at a very low frequency due to the finite gain of the error amplifier; however, its location is approximated at DC for the purposes of compensation. The other two poles and two zeros are located accordingly to stabilize the voltage-mode loop depending on the power stage complex poles and their quality factor, Q. Figure 34 illustrates a typical type-III compensator transfer function.

LM21215A 30152141.gifFigure 34. Type-III Compensation Network Bode Plot

As seen in Figure 34, the two compensator zeros located at (fLC/2, fLC) provide a phase boost. This mitigates the effect of the phase loss from the output filter. The compensation network also adds two poles to the system. One pole is located at the output capacitor ESR zero (fESR) and the other pole is at half the switching frequency (FSW/2) to roll off the high frequency response.

The dependency of the pole and zero locations on the compensation components is described as follows:

LM21215A q_F_PoleZero_nosb87.gif

The output capacitance, COUT, depends on capacitor chemistry and bias voltage. For multi-layer ceramic capacitors (MLCC), the total capacitance degrades as the DC bias voltage is increased. To accurately calculate and optimize the compensation network, it is advisable to determine the effective capacitance of the output capacitors when biased at the output voltage.

The example given here is the total output capacitance using three MLCC output capacitors biased at 1.2 V, as seen in the typical application schematic of Figure 28. 50% capacitance derating is assumed.

NOTE

It is more conservative, from a stability standpoint, to err on the side of a lower output capacitance in the compensation calculations rather than a higher, as this will result in a lower bandwidth but increased phase margin.

First, choose a resistance for RFB1, a typical value being 10 kΩ. From this, calculate the resistance of RC1 using Equation 14 to set the mid-band gain such that the desired crossover frequency is achieved.

Equation 14. LM21215A q_Rc1_nosb87.gif

Next, calculate the capacitance of CC1 by placing a zero at half of the LC double pole frequency (fLC):

Equation 15. LM21215A q_Cc1_nosb87.gif

Now calculate CC2 to place a pole at half of the switching frequency and RC2 to place the second zero at the LC double pole frequency:

Equation 16. LM21215A q_Cc2_nosb87.gif
Equation 17. LM21215A q_Rc2_nosb87.gif

Last, derive capacitance of CC3 to place a pole at the same frequency as the output capacitor ESR zero:

Equation 18. LM21215A q_Cc3_nosb87.gif

An illustration of the total loop response is seen in Figure 35.

LM21215A 30152139.gifFigure 35. Loop Response

It is important to verify the stability either by observing the load transient response or by using a network analyzer. A phase margin between 45° and 70° is usually desired for voltage-mode converter circuits. Excessive phase margin causes slow system response to load transients whereas low phase margin leads to an oscillatory load transient response. If the peak deviation of the load transient response is larger than required, increasing fcrossover and recalculating the compensation components may help but usually at the expense of phase margin.

Table 2. Bill of Materials (VIN = 3.3 V to 5.5 V, VOUT = 1.2 V, IOUT = 15 A, fSW = 500 kHz)

REF DES DESCRIPTION VENDOR PART NUMBER QUANTITY
CF CAP, CERM, 1 µF, 10 V, ±10%, X7R, 0603 MuRata GRM188R71A105KA61D 1
CIN1, CIN2, CIN3, CO1, CO2, CO3 CAP, CERM, 100 µF, 6.3 V, ±20%, X5R, 1206 MuRata GRM31CR60J107ME39L 6
CC1 CAP, CERM, 1800 pF, 50 V, ±5%, C0G/NP0, 0603 TDK C1608C0G1H182J 1
CC2 CAP, CERM, 68 pF, 50 V, ±5%, C0G/NP0, 0603 TDK C1608C0G1H680J 1
CC3 CAP, CERM, 820 pF, 50 V, ±5%, C0G/NP0, 0603 TDK C1608C0G1H821J 1
CSS CAP, CERM, 0.033 µF, 16 V, ±10%, X7R, 0603 MuRata GRM188R71C333KA01D 1
LF Inductor, Powdered Iron, 560 nH, 27.5A, 1.8 mΩ, SMD Vishay Dale IHLP4040DZERR56M01 1
RF RES, 1 Ω, 5%, 0.1 W, 0603 Vishay Dale CRCW06031R00JNEA 1
RC1 RES, 9.31 kΩ, 1%, 0.1 W, 0603 Vishay Dale CRCW06039K31FKEA 1
RC2 RES, 165 Ω, 1%, 0.1 W, 0603 Vishay Dale CRCW0603165RFKEA 1
RFB1, RFB2, RPGOOD RES, 10 kΩ, 1%, 0.1 W, 0603 Vishay Dale CRCW060310K0FKEA 3
U1 LM21215A Synchronous Buck Regulator TI LM21215AMH-1/NOPB 1