SNOSB87D March   2011  – May 2019 LM21215A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
    1.     Efficiency at 2.5 V, 500 kHz
  3. 3 Description
    1.     Typical Application Circuit
      1.      Device Images
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Precision Enable
      2. 7.3.2 Input Voltage UVLO
      3. 7.3.3 Soft-Start Capability
      4. 7.3.4 PGOOD Indicator
      5. 7.3.5 Frequency Synchronization
      6. 7.3.6 Current Limit
      7. 7.3.7 Short Circuit Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Light-Load Operation
      2. 7.4.2 Overvoltage and Undervoltage Handling
      3. 7.4.3 Thermal Shutdown
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application 1
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2 Output Voltage Setpoint
          3. 8.2.1.2.3 Precision Enable
          4. 8.2.1.2.4 Filter Inductor Selection
          5. 8.2.1.2.5 Output Capacitor Selection
          6. 8.2.1.2.6 Input Capacitor Selection
          7. 8.2.1.2.7 Control Loop Compensation
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical Application 2
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Compact PCB Layout for EMI Reduction
      2. 10.1.2 Thermal Design
      3. 10.1.3 Ground Plane Design
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Unless otherwise stated, the following conditions apply: VPVIN = VAVIN= 5 V, TJ = 25°C. Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C and are provided for reference purposes only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SYSTEM
VFB Feedback voltage VIN = 2.95 V to 5.5 V TJ = –40°C to 125°C –1% 1% V
TJ = 25°C 0.6
ΔVOUT/ΔIOUT Load regulation 0.02% VOUT/A
ΔVOUT/ΔVIN Line regulation 0.1% VOUT/V
RDSON-HS High-side switch on-resistance ISW = 12 A TJ = –40°C to 125°C 9 mΩ
TJ = 25°C 7
RDSON-LS Low-side switch on-resistance ISW = 12 A TJ = –40°C to 125°C 6 mΩ
TJ = 25°C 4.3
ICLR HS rising switch current limit TJ = –40°C to 125°C 17.3 22.8 A
TJ = 25°C 20
ICLF LS falling switch current limit 14 A
VZX Zero-cross voltage –8 3 12 mV
IQ Operating quiescent current TJ = –40°C to 125°C 3 mA
TJ = 25°C 1.5
ISD Shutdown quiescent current VEN = 0 V TJ = –40°C to 125°C 70 µA
TJ = 25°C 50
VUVLO AVIN undervoltage lockout AVIN rising TJ = –40°C to 125°C 2.45 2.95 V
TJ = 25°C 2.70
VUVLOHYS AVIN undervoltage lockout hysteresis TJ = –40°C to 125°C 140 280 mV
TJ = 25°C 200
VTRACKOS SS/TRACK accuracy (VSS/TRK – VFB) 0 < VSS/TRK < 0.55 V TJ = –40°C to 125°C –10 20 mV
TJ = 25°C 6
ISS Soft-start pin source current TJ = –40°C to 125°C 1.3 2.5 µA
TJ = 25°C 1.9
tINTSS Internal soft-start ramp to Vref SS/TRK open TJ = –40°C to 125°C 350 675 µs
TJ = 25°C 500
tRESETSS Device reset to soft-start ramp TJ = –40°C to 125°C 50 200 µs
TJ = 25°C 110
OSCILLATOR
fSYNCR SYNC frequency range TJ = –40°C to 125°C 300 1500 kHz
fDEFAULT Default (no SYNC signal) frequency TJ = –40°C to 125°C 475 525 kHz
TJ = 25°C 500
tSY_SW Time from VSYNC falling to VSW rising 200 ns
tSY_MIN Minimum SYNC pulse width, high or low 100 ns
tHSBLANK HS OCP blanking time Rising edge of SW to ICLR comparison 55 ns
tLSBLANK LS OCP blanking time Falling edge of SW to ICLF comparison 400 ns
tZXBLANK Zero cross blanking time Falling edge of SW to VZX comparison 120 ns
tMINON Minimum HS on-time 140 ns
ΔVRAMP PWM ramp peak-peak voltage 0.8 V
ERROR AMPLIFIER
VOL Error amplifier open-loop gain ICOMP = –65 µA to 1 mA 95 dB
GBW Error amplifier gain-bandwidth 11 MHz
IFB Feedback pin bias current VFB = 0.6 V 1 nA
ICOMPSRC COMP output source current 1 mA
ICOMPSINK COMP output sink current 65 µA
POWER GOOD
VOVP Overvoltage protection rising threshold VFB rising TJ = –40°C to 125°C 105% 120% VFB
TJ = 25°C 112.5%
VOVPHYS Overvoltage protection hysteresis VFB falling 2% VFB
VUVP Undervoltage protection rising threshold VFB rising TJ = –40°C to 125°C 82% 97% VFB
TJ = 25°C 90%
VUVPHYS Undervoltage protection hysteresis VFB falling 2.5% VFB
tPGDGL PGOOD deglitch low Time to PGOOD falling after OVP/UVP event 15 µs
tPGDGH PGOOD deglitch high Minimum low pulse 12 µs
RPGOOD PGOOD pulldown resistance TJ = –40°C to 125°C 10 40 Ω
TJ = 25°C 20
IPGOODLEAK PGOOD leakage current VPGOOD = 5 V 1 nA
LOGIC
VIHSYNC SYNC pin logic high 2 V
VILSYNC SYNC pin logic low 0.8 V
VIHENR EN pin rising threshold VEN Rising TJ = –40°C to 125°C 1.2 1.45 V
TJ = 25°C 1.35
VENHYS EN pin hysteresis TJ = –40°C to 125°C 50 180 mV
TJ = 25°C 110
IEN EN pin pullup current VEN = 0 V 2 µA
THERMAL SHUTDOWN
TTSD Thermal shutdown 165 °C
TTSD-HYS Thermal shutdown hysteresis 10 °C