SNVS639G December   2009  – December 2015 LM21305

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Synchronous DC-DC Switching Converter
      2. 8.3.2  Peak Current-Mode Control
      3. 8.3.3  Switching Frequency Setting and Synchronization
      4. 8.3.4  Light-Load Operation
      5. 8.3.5  Precision Enable
      6. 8.3.6  Device Enable, Soft-Start, and Pre-Bias Startup Capability
      7. 8.3.7  Peak Current Protection and Negative Current Limiting
      8. 8.3.8  PGOOD Indicator
      9. 8.3.9  Internal Bias Regulators
      10. 8.3.10 Minimum On-Time Considerations
    4. 8.4 Device Functional Modes
      1. 8.4.1 Overvoltage and Undervoltage Handling
      2. 8.4.2 Undervoltage Lockout (UVLO)
      3. 8.4.3 Thermal Protection
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Setting the Output Voltage
        2. 9.2.2.2  Calculating the Duty Cycle
        3. 9.2.2.3  Input Capacitors
        4. 9.2.2.4  AVIN Filter
        5. 9.2.2.5  Switching Frequency Selection
        6. 9.2.2.6  Filter Inductor
        7. 9.2.2.7  Output Capacitor
        8. 9.2.2.8  Efficiency Considerations
        9. 9.2.2.9  Load Current Derating When Duty Cycle Exceeds 50%
        10. 9.2.2.10 Control Loop Compensation
        11. 9.2.2.11 Compensation Components Selection
        12. 9.2.2.12 Plotting the Loop Gain
        13. 9.2.2.13 High Frequency Considerations
        14. 9.2.2.14 Bootstrap Capacitor
        15. 9.2.2.15 5V0 and 2V5 Capacitors
        16. 9.2.2.16 Maximum Ambient Temperature
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Compact PCB Layout for EMI Reduction
      2. 11.1.2 Ground Plane and Thermal Design Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
      2. 12.2.2 PCB Layout Resources
      3. 12.2.3 Resources for Thermal PCB Design
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Description (continued)

The LM21305 offers flexible system configuration with programmable switching frequency from 300 kHz to 1.5 MHz using one resistor or by external clock synchronization for beat-frequency-sensitive and multi-regulator applications. On-chip bias supply low-dropout (LDO) sub-regulators eliminate the need for an external bias power and simplify circuit board layout. The device also offers an internal soft-start to limit inrush current and provide monotonic startup capability into unbiased and pre-biased loads, integrated boot diodes, cycle-by-cycle current limiting, and thermal shutdown. Peak current-mode control with a high-gain error amplifier maintains stability throughout the entire input voltage and load current ranges, enabling excellent line and load transient response.

The LM21305 features internal output overvoltage protection (OVP) and overcurrent protection (OCP) circuits for increased system reliability. An integrated open-drain, PGOOD indicator provides output voltage monitoring, power-rail sequencing capability, and fault indication. Other features include thermal shutdown with automatic recovery, low PWM minimum on-time, low shutdown quiescent current, and precision enable with hysteresis for programmable line undervoltage lockout (UVLO).