8.3.1 Synchronous DC-DC Switching Converter

The LM21305 employs a buck type (step-down) dc-dc converter architecture. The device uses many advanced features to achieve excellent voltage regulation and efficiency. This easy-to-use regulator has two integrated power MOSFET switches and is capable of supplying up to 5 A of continuous output current. The regulator uses peak current-mode control with slope compensation scaled with switching frequency to optimize stability and transient response over the entire output voltage and switching frequency ranges. Peak current-mode control also provides inherent line feed-forward, cycle-by-cycle current limiting, and easy loop compensation. The switching frequency is adjusted between 300 kHz and 1.5 MHz. The device can operate with a small external LC filter and still provides very low output voltage ripple. The precision internal voltage reference allows the output to be set as low as 0.598 V. Using an external compensation circuit, the regulator crossover frequency can be selected based on the switching frequency to provide fast line and load transient response.

The switching regulator is specifically designed for highly-efficient operation throughout the load range. Synchronous rectification yields high efficiency for low output voltage and heavy load current situations, whereas discontinuous conduction mode (DCM) and diode emulation mode (DEM) enable high-efficiency conversion at lighter load current conditions. Fault protection features include: high-side and low-side MOSFET current limiting, negative current limiting on the low-side MOSFET, overvoltage protection, and thermal shutdown. The device is available in a WQFN-28 package featuring an exposed pad to aid thermal dissipation. Use the LM21305 in numerous applications to efficiently step-down from a wide range of input rails: 3 V to 18 V.

8.3.2 Peak Current-Mode Control

In most applications, the peak current-mode control architecture used in the LM21305 requires only two external components to achieve a stable design. External compensation allows the user to set the crossover frequency and phase margin, thus optimizing the transient performance of the device. For duty cycles above 50%, all peak current-mode controlled buck converters require the addition of an additional ramp to avoid sub-harmonic oscillation. This linear ramp is commonly referred to as slope compensation. The amount of slope compensation in the LM21305 automatically changes depending on the switching frequency: the higher the switching frequency, the larger the slope compensation. This adaptive amplitude slope compensation feature facilitates use of smaller inductors in high-switching frequency applications where higher power density is critical.

8.3.3 Switching Frequency Setting and Synchronization

The LM21305 switching regulator operates over a frequency ranging from 300 kHz to 1.5 MHz. The switching frequency is set or controlled in two ways. One is by selecting the external resistor connected to the FREQ pin to set the internal free-running oscillator frequency that determines the switching frequency. Connect an external 100-pF capacitor, C_FRQ, from FREQ to AGND as a noise filter, as shown in Figure 19.

Figure 19. Switching Frequency Set by External Resistor

The other way is to synchronize the switching frequency to an external clock in the range of 300 kHz to 1.5 MHz. Apply the external clock through a 100-pF coupling capacitor, C_FRQ, as shown in Figure 20.

Figure 20. Switching Frequency Synchronized to the External Clock

The recommendations for the external clock include peak-to-peak voltage above 1.5 V, duty cycle between 20% and 80%, and an edge rate faster than 100 ns. Circuits that use an external clock must still use a resistor connected from FREQ to AGND. The external clock frequency must be within –10% to +50% of the free-running frequency set by R_FRQ. This arrangement allows the regulator to continue operating at approximately the same switching frequency if the external clock fails and the coupling capacitor on the clock side is grounded or pulled to logic high.

If the external clock fails low, timeout circuits prevent the high-side MOSFET from staying off for longer than 1.5 times the switching period, T_SW = 1 / F_SW. At the end of this timeout period, the regulator begins to switch at the frequency set by R_FRQ.

If the external clock fails high, timeout circuits again prevent the high-side MOSFET from staying off longer than 1.5 times the switching period. After this timeout period, the internal oscillator takes over and switches at a fixed 1 MHz until the voltage on the FREQ pin has decayed to approximately 0.6 V. This decay follows the time constant of C_FRQ and R_FRQ and, when complete, the regulator switches at the frequency set by R_FRQ.

8.3.4 Light-Load Operation

The LM21305 offers increased efficiency at light loads by allowing discontinuous conduction mode (DCM). When the load current is less than half of the inductor ripple current the device enters DCM, thus preventing negative inductor current. The output current at the critical conduction boundary is calculated according to Equation 1:

Equation 1.

where

• D is the duty cycle of the high-side MOSFET, equal to the high-side MOSFET on-time divided by the switching period

For more details, see the Calculating the Duty Cycle subsection in the Detailed Design Procedure section. Several diagrams are provided in Figure 21 that illustrate continuous conduction mode (CCM), discontinuous conduction mode (DCM), and the boundary condition. In DCM, whenever the inductor current reaches zero the SW node becomes high impedance. Ringing occurs on this pin as a result of the LC tank circuit formed by the inductor and the effective parasitic capacitance at the switch node. At very light loads, usually below 100 mA, several pulses are skipped in between switching cycles, effectively reducing the switching frequency and further improving light-load efficiency.

Figure 21. CCM and DCM Operation

8.3.5 Precision Enable

The enable (EN) pin allows the output of the device to be enabled or disabled with an external control signal. This pin is a precision analog input that enables the device when the voltage exceeds 1.2 V (typical). The EN pin has 200 mV (typical) of hysteresis and disables the output when the enable voltage falls below 1.0 V (typical). If the EN pin is not used, pull this pin up to AVIN via a 10-kΩ to 100-kΩ resistor. Given that EN has a precise turn-on threshold, use an external resistor divider network from an external voltage to configure the device to turn on at a precise voltage. The precision enable circuits remains active even when the device is disabled. From Figure 22, calculate the turn-on voltage with a divider using Equation 2:

Equation 2.

Figure 22. Use an External Resistor Divider to Set the EN Threshold

8.3.6 Device Enable, Soft-Start, and Pre-Bias Startup Capability

The LM21305 can be turned off by removing AVIN or by pulling the EN pin low. To enable the device, the EN pin must be high with the presence of AVIN and PVIN. When enabled, the device engages the internal soft-start circuit. The soft-start feature allows the regulator output to gradually reach the steady-state operating point, thus reducing stresses on the input supply and controlling startup current. Soft-start begins at the rising edge of EN with AVIN above the UVLO level. PVIN must be high when soft-start begins. The LM21305 allows AVIN to be higher than PVIN, or PVIN higher than AVIN, provided that both voltages are within their operating ranges.

Soft-start of the LM21305 is controlled internally, and 2.7 ms is typically required to finish the soft-start sequence. PGOOD transitions high after soft-start is complete.

The LM21305 is in a pre-biased state when the device initiates startup with an output voltage greater than zero. This condition often occurs in multi-rail applications, such as when powering an field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), or digital signal processor (DSP) loads. In these applications, the output can be pre-biased through parasitic conduction paths from one supply rail to another. Even though the LM21305 is a synchronous converter, the device does not pull the output low when a pre-bias condition exists. During startup, the LM21305 is in diode emulation mode with the low-side MOSFET turned off when zero crossing of the inductor current is detected.

8.3.7 Peak Current Protection and Negative Current Limiting

The LM21305 switching regulator detects the peak inductor current and limits it to 7 A, typical. To determine the average current from the peak current, the inductor size, input and output voltage, and switching frequency must be known. The average current limit is found from Equation 3:

Equation 3.

When the peak inductor current sensed in the high-side MOSFET reaches the current limit threshold, an overcurrent event is triggered, the high-side MOSFET turns off and the low-side MOSFET turns on, allowing the inductor current to ramp down until the next switching cycle. When the high-side overcurrent condition persists, the output voltage is decreased by the reduced high-side MOSFET on-time.

In cases such as output short-circuit or when high-side MOSFET minimum on-time conditions are reached, the high-side MOSFET current limiting may not be sufficient to limit the inductor current. The LM21305 features an additional low-side MOSFET current limit to prevent the inductor current from running away. The low-side MOSFET current limit, 8 A typical, is set higher than the high-side current limit. When the low-side MOSFET current is higher than the limit level, PWM pulses are skipped until a low-side overcurrent is not detected during the entire low-side MOSFET conduction time. Normal PWM switching subsequently occurs when the condition is removed. High-side and low-side MOSFET current protections result in a current limit that does not aggressively foldback for brief overcurrent events, and at the same time provides frequency and voltage foldback protection during hard short-circuit conditions. The low-side MOSFET also has a negative current limit, –4.1 A typical, for secondary protection that can engage during response to overvoltage events. If the negative current limit is triggered, the low-side MOSFET is turned off. The negative current is forced to go through the high-side MOSFET body diode and quickly reduces.

8.3.8 PGOOD Indicator

To implement an open-drain, power-good function for sequencing and fault detection, use the PGOOD pin of the LM21305. The PGOOD open-drain MOSFET is pulled low during output undervoltage and overvoltage, UVLO, and thermal shutdown. The PGOOD function has a 16-µs glitch filter to prevent false-flag operation for short excursions in the output voltage, such as during line and load transients. When the FB voltage is typically within –7% to 9.5% of the reference voltage, PGOOD is high. The thresholds track with the output voltage because the PGOOD comparator and the regulation loop share the same reference. Pull PGOOD high with an external resistor (10 kΩ to 100 kΩ is recommended) to an external logic supply. PGOOD can also be pulled-up to either the 5V0 rail or to the output voltage through an appropriate resistor, as desired. Tie PGOOD to AGND if the function is not required.

8.3.9 Internal Bias Regulators

The LM21305 contains two internal low dropout (LDO) regulators to produce internal driving and bias voltage rails from AVIN. One LDO produces 5 V to power the internal MOSFET drivers, the other LDO produces 2.5 V to power the internal bias circuitry. Bypass both the 5V0 or 2V5 LDOs to the analog ground (AGND) with an external ceramic capacitor (1 μF and 0.1 μF are recommended, respectively). Good bypassing is necessary to supply the high transient currents required by the power MOSFET gate drivers. Applications with high input voltage and high switching frequency increase die temperature because of the higher power dissipation within the LDOs. Connecting a load to the 5V0 or 2V5 pins is not recommended because doing so degrades their driving capability to internal circuitry, further pushing the LDOs into their RMS current ratings and increasing power dissipation and die temperature.

The LM21305 allows AVIN to be as low as 3 V, which makes the voltage at the 5V0 LDO lower than 5 V. Low supply voltage at the MOSFET drivers increases on-state resistance of the high-side and low-side power MOSFETs and reduces efficiency of the regulator. When AVIN is between 3 V and 5.5 V, the best practice is to short the 5V0 pin to AVIN to avoid the voltage drop on the internal LDO. However, the device can be damaged if the 5V0 pin is pulled to a voltage higher than 5.5 V. For efficiency considerations, use AVIN = 5 V if possible. When AVIN is above 5 V, reduced efficiency can be observed at light load because of the power loss of the LDOs. When AVIN is close to 3 V, increased MOSFET on-state resistance can reduce efficiency at high load currents.

8.3.10 Minimum On-Time Considerations

Minimum on-time, T_ON-MIN, is the smallest duration of time that the high-side MOSFET conducts, typically 70 ns in the LM21305. In CCM operation, the minimum on-time limit corresponds to a minimum duty cycle as shown in Equation 4:

Equation 4.

The minimum on-time becomes relevant when operating simultaneously at high input voltage and high switching frequency. As Equation 4 shows, reducing the operating frequency alleviates the minimum on-time constraint. For a given switching frequency and output voltage, the maximum PVIN is approximated by Equation 5:

Equation 5.

Similarly, if the input voltage is fixed, the maximum switching frequency without reaching the minimum on-time constraint is found by Equation 6:

Equation 6.

In rare cases where steady-state operation at minimum duty cycle is unavoidable, the regulator automatically skips cycles to keep V_OUT regulated, similar to light-load DCM operation.

8.4.1 Overvoltage and Undervoltage Handling

The LM21305 has built-in undervoltage protection (UVP) and overvoltage protection (OVP) using FB voltage comparators to control the power MOSFETs. The rising OVP threshold is typically set at 109.5% of the nominal voltage setpoint. Whenever excursions occur in the output voltage above the OVP threshold, the device terminates the present on-pulse, turns on the low-side MOSFET, and pulls PGOOD low. The low-side MOSFET remains on until either the FB voltage falls back into regulation or the inductor current zero-cross is detected. If the output reaches the falling UVP threshold, typically 88.8% of the nominal setpoint, the device continues switching and PGOOD is asserted and pulls low. As detailed in the PGOOD Indicator section, PGOOD has 16 μs of built-in deglitch time to both the rising and falling edges to avoid false tripping during transient glitches. OVP is disabled during soft-start to prevent false triggering.

8.4.2 Undervoltage Lockout (UVLO)

The LM21305 has a built-in undervoltage lockout (UVLO) protection circuit that prevents the device from switching until the AVIN voltage reaches 2.93 V (typical). The UVLO threshold has typically 195 mV of hysteresis that keeps the device from responding to power-on glitches during startup.

8.4.3 Thermal Protection

Internal thermal shutdown circuitry is provided to protect the LM21305 in the event that the maximum junction temperature is exceeded. When activated, typically at 160°C, the LM21305 turns off the power MOSFETs and resets soft-start. After the junction temperature cools to approximately 150°C, the LM21305 starts up using the normal startup routine.